This paper studies the performance of a coded convolutional spreading CDMA system with cyclic prefix (CS-CDMA/CP) combined with the zero correlation zone code generated from the M-sequence (M-ZCZ code) for downlink transmission over a multipath fast fading channel. In particular, we propose a new pilot-aided channel estimation scheme based on the shift property of the M-ZCZ code and show the robustness of the scheme against fast fading through comparison with the W-CDMA system empolying time-multiplexed pilot signals.

We have developed a one-to-many eigenvoice conversion (EVC) system that allows us to convert a single source speaker's voice into an arbitrary target speaker's voice using an eigenvoice Gaussian mixture model (EV-GMM). This system is capable of effectively building a conversion model for an arbitrary target speaker by adapting the EV-GMM using only a small amount of speech data uttered by the target speaker in a text-independent manner. However, the conversion performance is still insufficient for the following reasons: 1) the excitation signal is not precisely modeled; 2) the oversmoothing of the converted spectrum causes muffled sounds in converted speech; and 3) the conversion model is affected by redundant acoustic variations among a lot of pre-stored target speakers used for building the EV-GMM. In order to address these problems, we apply the following promising techniques to one-to-many EVC: 1) mixed excitation; 2) a conversion algorithm considering global variance; and 3) adaptive training of the EV-GMM. The experimental results demonstrate that the conversion performance of one-to-many EVC is significantly improved by integrating all of these techniques into the one-to-many EVC system.

Break arcs are generated between electrical contacts in a DC 42 V resistive circuit. Contact materials are Ag/SnO2 and Ag/ZnO. Circuit current when contacts are closed is varied from 5 A to 21 A. The radial magnetic field to drive break arcs is formed between the contact gap with a permanent magnet embedded in the cathode. The arc motion is observed with a high-speed camera. Experimental results with the magnet are compared with those without the magnet. Following results are shown. Similar experimental results to pure silver contacts are obtained for Ag/SnO2 and Ag/ZnO contact pairs. The rotational motion of the break arcs and the shortening effect of the arc duration are confirmed. The ring-shaped, wide and uniform traces are observed on the contact surfaces after break operations. This result shows the prevention effect of local erosion of electrical contacts and the reduction of total amount of contact erosion. The rotational frequency f is increased with the increase of the arc current Iarc. These results for Ag/SnO2 and Ag/ZnO contact pairs are similar to the results for pure silver contacts in our previous experiments. The rotational frequency of the break arc for the Ag/SnO2 and Ag/ZnO contacts is lower than that for the pure silver contacts.

In this letter, a neural network (NN) for peak power reduction of an orthogonal frequency-division multiplexing (OFDM) signal is improved in order to suppress its computational complexity. Numerical experiments show that the amount of IFFTs in the proposed NN can be reduced to half, and its computational time can be reduced by 21.5% compared with a conventional NN. In comparison with the SLM, the proposed NN is effective to achieve high PAPR reduction and it has an advantage over the SLM under the equal computational condition.

We present a session initiation protocol (SIP) network design for a voice-over-IP network to prevent congestion caused by people calling friends and family after a disaster. The design increases the capacity of SIP servers in a network by using all of the SIP servers equally. It takes advantage of the fact that equipment for voice data packets is different from equipment for signaling packets in SIP networks. Furthermore, the design achieves simple routing on the basis of telephone numbers. We evaluated the performance of our design in preventing congestion through simulation. We showed that the proposed design has roughly 20 times more capacity, which is 57 times the normal load, than the conventional design if a disaster were to occur in Niigata Prefecture struck by the Chuetsu earthquake in 2004.

This paper proposes a method of correcting annotation errors in a treebank. By using a synchronous grammar, the method transforms parse trees containing annotation errors into the ones whose errors are corrected. The synchronous grammar is automatically induced from the treebank. We report an experimental result of applying our method to the Penn Treebank. The result demonstrates that our method corrects syntactic annotation errors with high precision.

This paper presents a Pulse-Width Modulation (PWM) pre-emphasis technique which utilizes time-domain information processing to increase the data rate for a given bandwidth of interconnection. The PWM pre-emphasis method does not change the pulse amplitude as for conventional FIR pre-emphasis, but instead exploits timing resolution. This fits well with recent CMOS technology trends toward higher switching speeds and lower supply voltage. We discuss multiple-valued data transmission based on time-domain pre-emphasis techniques in consideration of higher-order channel effects. Also, a new data-dependent adaptive time-domain pre-emphasis technique is proposed to compensate for the data-dependent jitter.

A unipolar n-n heterostrucuture diode is developed in the InP material system. The electronic barrier is formed by a saw tooth type of conduction band bending which consists of a quaternary In0.52(AlyGa1-y)0.48As layer with 0 < y < ymax. This barrier is lattice matched for all y to InP and is embedded between two n+-InGaAs layers. By varying the maximum Al-content from ymax,1 = 0.7 to ymax,2 = 1 a variable barrier height is formed which enables a diode-type I-V characteristic by epitaxial design with an adjustable current density within 3 orders of magnitude. The high current density of the diode with the lower barrier height (ymax,1 = 0.7) makes it suitable for high frequency applications at low signal levels. RF measurements reveal a speed index of 52 ps/V at VD = 0.15 V. The device is investigated for RF-to-DC power conversion in UHF RFID transponders with low-amplitude RF signals.

Novel thermopiles based on modulation doped AlGaAs/InGaAs, AlGaN/GaN, and ZnMgO/ZnO heterostructures are proposed and designed for the first time, for uncooled infrared image sensor application. These devices are expected to offer high performances due to both the superior Seebeck coefficient and the excellently high mobility of 2DEG and 2DHG due to high purity channel layers at the heterojunction interface. The AlGaAs/InGaAs thermopile has the figure-of-merit Z of as large as 1.110-2/K (ZT = 3.3 over unity at T = 300 K), and can be realized with a high responsivity R of 15,200 V/W and a high detectivity D* of 1.8109 cmHz1/2/W with uncooled low-cost potentiality. The AlGaN/GaN and the ZnMgO/ZnO thermopiles have the advantages of high sheet carrier concentration due to their large polarization charge effects (spontaneous and piezo polarization charges) as well as of a high Seebeck coefficient due to their strong phonon-drag effect. The high speed response time τ of 0.9 ms with AlGaN/GaN, and also the lower cost with ZnMgO/ZnO thermopiles can be realized. The modulation-doped heterostructure thermopiles presented here are expected to be used for uncooled infrared image sensor applications, and for monolithic integrations with other photon detectors such as InGaAs, GaN, and ZnO PiN photodiodes, as well as HEMT functional integrated circuit devices.

This letter presents a theoretical analysis of the Parallel Iterative Matching (PIM)'s dynamics with multiple iterations used in an input-buffered packet switch. In our approach, by carefully categorizing all unmatched patterns into several representative patterns after each iteration, probabilities of accumulated matched pairs in a recursive manner are successfully obtained. Numerical evaluations of the analytical formulas are performed.

The paper demonstrates a novel multiple-valued logic (MVL) design using a three-peak negative differential resistance (NDR) circuit, which is made of several Si-based metal-oxide-semiconductor field-effect-transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT) devices. Specifically, this three-peak NDR circuit is biased by two switch-controlled current sources. Compared to the traditional MVL circuit made of resonant tunneling diode (RTD), this multiple-peak MOS-HBT-NDR circuit has two major advantages. One is that the fabrication of this circuit can be fully implemented by the standard BiCMOS process without the need for molecular-beam epitaxy system. Another is that we can obtain more logic states than the RTD-based MVL design. In measuring, we can obtain eight logic states at the output according to a sequent control of two current sources on and off in order.

One-tap frequency-domain equalization (FDE) based on the minimum mean square error (MMSE) criterion can significantly improve the bit error rate (BER) performance of single-carrier (SC) transmission in a frequency-selective fading channel. However, a big performance gap from the theoretical lower bound still exists due to the presence of residual inter-symbol interference (ISI) after MMSE-FDE. In this paper, we point out that the frequency-domain received SC signal can be expressed using the matrix representation similar to the multiple-input multiple-output (MIMO) multiplexing and therefore, signal detection schemes developed for MIMO multiplexing, other than simple one-tap MMSE-FDE, can be applied to SC transmission. Then, for the reception of SC signals, we propose a new signal detection scheme, which combines FDE with MIMO signal detection, such as MMSE detection and Vertical-Bell Laboratories layered space-time architecture (V-BLAST) detection (we call this frequency-domain block signal detection). The achievable average BER performance using the proposed frequency-domain block signal detection is evaluated by computer simulation.

IEEE 802.15.4a standard enables location-aided routing or topology control in ZigBee networks, since it uses time-of-arrival (TOA)-based ranging technique. However, TOA based techniques may yield location error due to the non-line-of-sight (NLOS) effects, and hence degrade the network performance. In this letter, we demonstrate the impact of NLOS on the localization performance and propose a location error detection and compensation algorithm for IEEE 802.15.4a networks. The proposed algorithm detects NLOS by using the min-max algorithm and compensates the location error by using the Kalman filter. Experimental results show that the proposed algorithm significantly reduces the localization errors in indoor environments.

Drain collapse in AlGaN/GaN HFET is analyzed using a two-dimensional device simulator. Two-step saturation is obtained, assuming hole-trap type surface states on the AlGaN surface and a short negative-charge-injected region at the drain side of the gate. Due to the surface electric potential pinning by the surface traps, the negative charge injected region forms a constant potential like in a metal gate region and it acts as an FET with a virtual gate. The electron concentration profile reveals that the first saturation occurs by pinch-off in the virtual gate region and the second saturation occurs by the pinch-off in the metal gate region. Due to the short-channel effect of the virtual gate FET, the saturation current increases until it finally reaches the saturation current of the intrinsic metal gate FET. Current collapses with current degradation at the knee voltage in the I-V characteristics can be explained by the formation of the virtual gate.

Delay models for binary logic circuits have been proposed and clarified their mathematical properties. Kleene's ternary logic is one of the simplest delay models to express transient behavior of binary logic circuits. Goto first applied Kleene's ternary logic to hazard detection of binary logic circuits in 1948. Besides Kleene's ternary logic, there are many delay models of binary logic circuits, Lewis's 5-valued logic etc. On the other hand, multiple-valued logic circuits recently play an important role for realizing digital circuits. This is because, for example, they can reduce the size of a chip dramatically. Though multiple-valued logic circuits become more important, there are few discussions on delay models of multiple-valued logic circuits. Then, in this paper, we introduce a delay model of multiple-valued logic circuits, which are constructed by Min, Max, and Literal operations. We then show some of the mathematical properties of our delay model.

A multiple-valued current-mode (MVCM) circuit using current-flow control is proposed for a power-greedy sequential linear-array system. Whenever operation is completed in processing element (PE) at the present stage, every possible current source in the PE at the previous stage is cut off, which greatly reduces the wasted power dissipation due to steady current flows during standby states. The completion of the operation can be easily detected using "operation monitor" that observes input and output signals at latches, and that generates control signal immediately at the time completed. Since the wires of data and control signals are shared in the proposed MVCM circuit, no additional wires are required for current-flow control. In fact, it is demonstrated that the power consumption of the MVCM circuit using the proposed method is reduced to 53 percent in comparison with that without current-source control.

This paper proposes a high-speed architecture to realize two-variable numeric functions. It represents the given function as an edge-valued multiple-valued decision diagram (EVMDD), and shows a systematic design method based on the EVMDD. To achieve a design, we characterize a numeric function f by the values of l and p for which f is an l-restricted Mp-monotone increasing function. Here, l is a measure of subfunctions of f and p is a measure of the rate at which f increases with an increase in the dependent variable. For the special case of an EVMDD, the EVBDD, we show an upper bound on the number of nodes needed to realize an l-restricted Mp-monotone increasing function. Experimental results show that all of the two-variable numeric functions considered in this paper can be converted into an l-restricted Mp-monotone increasing function with p=1 or 3. Thus, they can be compactly realized by EVBDDs. Since EVMDDs have shorter paths and smaller memory size than EVBDDs, EVMDDs can produce fast and compact NFGs.

In this letter, we propose a novel approach to estimate three different kinds of phone mismatch penalty matrices for two-stage keyword spotting. When the output of a phone recognizer is given, detection of a specific keyword is carried out through text matching with the phone sequences provided by the specified keyword using the proposed phone mismatch penalty matrices. The penalty matrices associated with substitution, insertion and deletion errors are estimated from the training data through deliberate error generation. The proposed approach has shown a significant improvement in a Korean continuous speech recognition task.

Dynamically Programmable Gate Arrays (DPGAs) provide more area-efficient implementations than conventional Field Programmable Gate Arrays (FPGAs). One of typical DPGA architectures is multi-context architecture. An DPGA based on multi-context architecture is Multi-Context FPGA (MC-FPGA) which achieves fast switching between contexts. The problem of the conventional SRAM-based MC-FPGA is its large area and standby power dissipation because of the large number of configuration memory bits. Moreover, since SRAM is volatile, the SRAM-based multi-context FPGA is difficult to implement power-gating for standby power reduction. This paper presents an area-efficient and nonvolatile multi-context switch block architecture for MC-FPGAs based on a ferroelectric-capacitor functional pass-gate which merges a multiple-valued threshold function and a nonvolatile multiple-valued storage. The test chip for four contexts is fabricated in a 0.35 µm-CMOS/0.60 µm-ferroelectric-capacitor process. The transistor count of the proposed multi-context switch block is reduced to 63% in comparison with that of the SRAM-based one.

A fine-grain bit-serial multiple-valued reconfigurable VLSI based on logic-in-control architecture is proposed for effective use of the hardware resources. In logic-in-control architecture, the control circuits can be merged with the arithmetic/logic circuits, where the control and arithmetic/logic circuits are constructed by using one or multiple logic blocks. To implement the control circuit, only one state in a state transition diagram is allocated to one logic block, which leads to reduction of the complexity of interconnections between logic blocks. The fine-grain logic block is implemented based on multiple-valued current-mode circuit technology. In the fine-grain logic block, an arbitrary 3-variable binary function can be programmed by using one multiplexer and two universal literal circuits. Three-variable binary functions are used to implement the control circuit. Moreover, the hardware resources can be utilized to construct a bit-serial adder, because full-adder sum and carry can be realized by programming in the universal literal circuit. Therefore, the logic block can be effectively reconfigured for arithmetic/logic and control circuits. It is made clear that the hardware complexity of the control circuit in the proposed reconfigurable VLSI can be reduced in comparison with that of the control circuit based on a typically sequential circuit in the conventional FPGA and the fine-grain field-programmable VLSI reported until now.