We propose a new tableau construction which builds an FSM, instead of a Kripke structure, from a formula in a class of temporal logic named ASTL. This FSM is a maximal model of the formula under the preorder derived from simulation relations. Additionally, we propose a method using the tableaus to build controllers in a certain topology of interconnected FSMs. We can use ASTL to describe the desired behaviors of the control system. This method is applicable to generating digital circuits. Moreover, this method accepts a wider range of specifications than conventional methods.

Accurate estimating or measuring the intake manifold absolute pressure plays an important role in automobile engine control. In order to achieve the real-time estimation of the absolute pressure, the high accuracy and high speed processing ability are required for automobile engine control systems. Therefore, in this paper, an analog method is discussed and a fully integrated analog circuit is proposed to simulate automobile intake systems. Furthermore, a novel behavioral macromodeling is proposed for the analog circuit design. With the analog circuit, the intake manifold absolute pressure, which plays an important role for the effective automobile engine control, can be accurately estimated or measured in real time.

For more efficient data transmissions, a new MLP/BP-based channel equalizer is proposed to compensate for multi-path fading in wireless applications. In this work, for better system performance, we apply the soft output and the soft feedback structure as well as the soft decision channel decoding. Moreover, to improve packet error rate (PER) and bit error rate (BER), we search for the optimal scaling factor of the transfer function in the output layer of the MLP/BP neural networks and add small random disturbances to the training data. As compared with the conventional MLP/BP-based DFEs and the soft output MLP/BP-based DFEs, the proposed MLP/BP-based soft DFEs under multi-path fading channels can improve over 3-0.6 dB at PER=10-1 and over 3.3-0.8 dB at BER=10-3.

This paper addresses the issue of deafness in MAC (Medium Access Control) protocols for wireless ad hoc networks using directional antennas. Directional antennas are expected to provide significant improvements over omni-directional antennas in ad hoc networks, such as high spatial reuse and range extension. Recently, several MAC protocols using directional antennas, typically referred to as directional MAC protocols, have been proposed for ad hoc networks. However, directional MAC protocols inherently introduce new kinds of problems arising from directivity. One major problem is deafness, caused by a lack of state information of neighbor nodes, whether idle or busy. This paper proposes DMAC/DA (Directional MAC with Deafness Avoidance) to overcome the deafness problem. DMAC/DA modifies the previously proposed MAC protocol, MDA (MAC protocol for Directional Antennas), to reduce the number of control messages and also maintain the ability to handle deafness. In DMAC/DA, WTS (Wait To Send) frames are simultaneously transmitted by the transmitter and the receiver after the successful exchange of directional RTS (Request To Send) and CTS (Clear To Send) to notify the on-going communication to potential transmitters that may experience deafness. The experimental results show that DMAC/DA outperforms existing directional MAC protocols, such as DMAC (Directional MAC) and MDA, in terms of throughput, control overhead and packet drop ratio under the different values of parameters such as the number of flows and the number of beams. In addition, qualitative evaluation of 9 MAC protocols is presented to highlight the difference between DMAC/DA and existing MAC protocols.

We have successfully applied Generalized Multiprotocol Label Switching (GMPLS) architecture to the Wavelength Assignment Photonic Switching System (WAPS) to create an internet access system that can provide, between terminals, not only conventional best-effort type of IP packet forwarding, but also high-speed and Quality of Service (QoS)-guaranteed IP forwarding. In this paper the system architecture, system specifications, and system hardware/software implementations are described.

Under the assumption that clock can be inputted to each register at an arbitrary timing, the minimum feasible clock period can be determined if delays between registers are given. This minimum feasible clock period might be reduced by register relocation maintaining the circuit behavior and topology. In this paper, we propose a gate-level register relocation method to reduce the minimum feasible clock period. The proposed method is a greedy local circuit modification method. We prove that the proposed method achieves the clock period achieved by retiming with delay decomposition, if the delay of each element in the circuit is unique. Experiments show that the computation time of the proposed method and the number of registers of a circuit obtained by the proposed method are smaller than those obtained by the retiming method in the conventional synchronous framework.

Transitions between a post-wall waveguide and a microstrip line are proposed as the key components for cost-effective millimeter-wave modules. A transition with a coaxial structure is investigated for LTCC laminated layers and 11.3% bandwidth for the reflection smaller than -15 dB is realized in 60 GHz band. The overall connector loss with 1 cm post-wall would be about 0.8 dB. The degradation due to fabrication error is also assessed. The transition in LTCC substrate fulfills electrical and manufacturing demands in millimeter-wave bands.

Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose low power adders that adaptively select supply voltages based on the input vector patterns. First, we apply the proposed scheme to the Ripple Carry Adder (RCA). A prototype design by a 0.18 µm CMOS technology shows that the Adaptive VDD 32-bit RCA achieves 25% power improvement over the conventional RCA with similar speed. The proposed adder cancels out the delay penalty, utilizing two innovative techniques: carry-skip techniques on the checking operands, and the use of Complementary Pass Transistor Logic (CPL) with dual supply voltage for level conversion. As an expansion to faster adder architectures, we extend the proposal to the Carry-Select Adders (CSA) composed of the RCA sub-blocks. We achieved 24% power improvement on the 128-bit CSA prototype over a conventional design. The proposed scheme also achieves stand-by leakage power reduction--for 32-bit and 128-bit Adaptive RCA and CSA, respectively, 62% and 54% leakage reduction was possible.

This paper describes a current-steering Digital-to-Analog Converter (IDAC) architecture with a novel switching scheme, designed for GPON Burst Mode Laser Drivers (BMLD) and realized in a 0.35 µm SiGe BiCMOS technology with 3.3 V power supply. The (4+6) segmented architecture of the proposed 10-bit IDAC is optimized for minimum DNL (Differential Nonlinearity). It combines a 4-bit MSBs (Most Significant Bits) unit-element sub-DAC and a 6-bit LSBs (Least Significant Bits) binary-weighted sub-DAC. A switching scheme based on this dedicated architecture yields a high monotony and a fast settling time. The linearity errors caused by systematic influences and random variations are reduced by the 2-D double centroid symmetrical architecture. Experimental results show that the DNL is below 0.5 LSB and that the settling time after the output current mirror is below 12 ns. Although the proposed IDAC architecture was designed for a BMLD chip, the design concept is generic and can be applied for developing other monotonic high-speed current-mode DACs.

All optical analog-to-digital converter consisting of an optical polarization modulator using nonlinear phase shift and switches based on polarization is proposed. The principle of operation is discussed using Jones matrix. Optical polarization states through the system and limit of resolution are evaluated. The resolution is optimized by maintaining the polarization state in the converter and refining the polarization of incident sampling signal. Parallel usage of converter modules is proposed to increase the dynamic range, where cyclic nature of optical phase plays an important roll. Application to photonic routing of our converter is also proposed.

This letter presents a simple scheme to transform colors to some representative classes for color information reduction. Then, the weighted distributions of color index histogram (CIH) and local binary pattern (LBP) are applied to measure the similarity of adjacent texture regions during the segmentation process. In addition, for improving the segmentation accuracy, an efficient boundary checking algorithm is proposed. The proposed method not only saves execution time but also segments the distinct texture regions correctly.

Manually collecting contexts of a target word and grouping them based on their meanings yields a set of word senses but the task is quite tedious. Towards automated lexicography, this paper proposes a word-sense discrimination method based on two modern techniques; EM algorithm and principal component analysis (PCA). The spherical Gaussian EM algorithm enhanced with PCA for robust initialization is proposed to cluster word senses of a target word automatically. Three variants of the algorithm, namely PCA, sGEM, and PCA-sGEM, are investigated using a gold standard dataset of two polysemous words. The clustering result is evaluated using the measures of purity and entropy as well as a more recent measure called normalized mutual information (NMI). The experimental result indicates that the proposed algorithms gain promising performance with regard to discriminate word senses and the PCA-sGEM outperforms the other two methods to some extent.

Heterogeneous distributed computing environments are well suited to meet the fast increasing computational demands. Task scheduling is very important for a heterogeneous distributed system to satisfy the large computational demands of applications. The performance of a scheduler in a heterogeneous distributed system normally has something to do with the dynamic task flow, that is, the scheduler always suffers from the heterogeneity of task sizes and the variety of task arrivals. From the long-term viewpoint it is necessary and possible to improve the performance of the scheduler serving the dynamic task flow. In this paper we propose a task scheduling method including a scheduling strategy which adapts to the dynamic task flow and a genetic algorithm which can achieve the short completion time of a batch of tasks. The strategy and the genetic algorithm work with each other to enhance the scheduler's efficiency and performance. We simulated a task flow with enough tasks, the scheduler with our strategy and algorithm, and the schedulers with other strategies and algorithms. We also simulated a complex scenario including the variant arrival rate of tasks and the heterogeneous computational nodes. The simulation results show that our scheduler achieves much better scheduling results than the others, in terms of the average waiting time, the average response time, and the finish time of all tasks.

A method for shortening of the settling time in all digital phase-locked loops is proposed. The method utilizes self monitoring to obtain the parameters necessary for feed-forward compensation. Analysis shows that by employing this technique both fast settling and good stability can be achieved simultaneously. Matlab and Verilog-AMS simulation shows that typical settling speed can be reduced to less than one tenth compared to a system without the feed-forward compensation, by merely employing the feed-forward compensation system. Further more a design example shows that this settling time can be decreased further to less than one fifteenth through design considerations when compared to a speed optimized phase-locked loop design system without direct reference feed-forward compensation.

Asymmetric Slope Dual Mode Differential Logic (ASDMDL) embodies high-speed dynamic and low-power static operations in a single design. Two-phase dual-rail logic signaling is used in a high-speed operation, where a logical evaluation is preceded by pre-charge, and it asserts one of the rails with an asymmetrically shortened rise transition to express a binary result. On the other hand, single-phase differential logic signaling eliminates pre-charge and leads to a low-power static operation. The operation mode is defined by the logic signaling styles, and no control signal is needed in the logic cell. The design of mixed CMOS and ASDMDL logic circuits can be automated with general logic synthesis and place-and-route techniques, since the physical ASDMDL cell is prepared in such a way to comply with a CMOS standard-cell design flow. A mixed ASDMDL/CMOS micro-processor in a 0.18-µm CMOS technology demonstrated 232 MHz operation, corresponding to 14% speed improvement over a full CMOS implementation. This was achieved by substituting ASDMDL cells for only 4% of the CMOS logic cells in data paths. The low-speed operation of ASDMDL at 100 MHz was nearly equivalent to that of CMOS. However, power consumption was reduced by 3% due to the use of ASDMDL complex logic cells. Area overhead was less than 4%.

In a typical installation of an 802.11 based WLAN (Wireless Local Area Network), mobile hosts would access the network through APs (Access Points), even when two mobile stations communicate within the same WLAN. Effectively, all the packets in a WLAN are required to forward through the AP according to the MAC (Medium Access Control) layer protocol. Since the AP has the same priority as the other mobile stations to access the channel, the AP usually becomes a bottleneck in WLANs and the network performance degrades significantly. In this paper, we propose a new MAC layer protocol for WLANs in order to improve the throughput performance. Theoretical analysis and simulation results show that our new protocol works much better in WLAN than the standard DCF.

This paper presents a novel threshold-based selection scheme to combine adaptive transmit antenna selection with an adaptive quadrature amplitude modulation (AQAM) for a spatial multiplexing (SM) multiple-input multiple-output (MIMO) system with linear receivers in practical uncorrelated and correlated channel conditions. The proposed scheme aims to maximize the average spectral efficiency (ASE) for a given bit error rate (BER) constraint and also to lower the hardware complexity. Our simulations are run on a general MIMO channel model, under the assumption that the channel state information (CSI) is known at the receiver and the adaptive control signaling can be perfectly fed back to the transmitter. We deploy the low rank-revealing QR (LRRQR) algorithm in transmit antenna subset selection. LRRQR is computationally less expensive than a singular value decomposition (SVD) based algorithm while the two algorithms achieve similar error rate performances. We show that both the conventional AQAM scheme (i.e., without adaptive transmit antenna selection) and the SM scheme perform poorly in a highly correlated channel environment. We demonstrate that our proposed scheme provides a well-behaved trade-off between the ASE and BER under various channel environments. The ASE (i.e., throughput) can be maximized with a proper choice of the channel quality threshold and AQAM mode switching threshold levels for a target BER.

In this paper, we examine the Interleaved Polling with Adaptive Cycle Time (IPACT) that was proposed to control upstream traffic for Gigabit Ethernet-PONs, a promising technology for the Fiber To The Home (FTTH). We analyzed the performance for the gated service and the limited service mathematically. To do this, the IPACT protocol was modeled as a polling system and analyzed by using mean-value analysis technique. The traffic arrival rate λ was divided into three regions, and each region was analyzed separately and merged appropriately by using an interpolation method. The average packet delay, average queue size, and average cycle time of both the gated service and the limited service were obtained through the analysis. In order to evaluate the accuracy of the mathematical analysis, discrete event simulation was performed for the IPACT protocol. Simulation results show the accuracy of the mathematical analysis. The analysis results can be widely used in the design of the FTTH system based on EPON, as the performance results in the present study can be obtained in a rather short time. We can design an appropriate system depending on various traffic conditions by adjusting system parameters, such as the number of users N, the maximum transfer window WMAX, and so on.

An edge-weighted directed graph is referred to as a network in this paper, and an edge operation is an operation that increases or decreases an edge weight. Decreasing an edge weight from the infinite to a finite value or increasing any edge weight from a finite one to the infinite corresponds to addition or deletion of this edge, respectively. The dynamic shortest path problem (DSPP for short) is defined by "Given any network with a specified vertex (denoted as s), and any sequence of edge operations, construct a shortest path tree of each network obtained by executing those edge operations one by one in the order of the sequence." As an application, fast routing for an interior network using link state protocols, such as OSPF and IS-IS, requires solving DSPP efficiently. In this paper, among as many existing algorithms as possible, including those which execute several edge operations simultaneously, fundamental and/or important algorithms are implemented and their capability is evaluated based on the results of computational experiments.

In order to introduce the burst firing, a nerve-cell dynamic feature, we extend the Inverse function Delayed model (ID model), which is the neuron model with ability to oscillate and has powerful ability on the information processing. This dynamics is discussed for the relation with the functional role of the brain and is characterized by repeated patterns of closely spaced action potentials. It is expected that the additional new characteristics add extra functions to neural networks. Using the relation between the ID model and reduced Hodgkin-Huxley model, we propose the neuron model with ability of burst. The proposed model excelled the ID model in solving the N-Queen problem. Additionally, the prototype chip for the burst ID model is implemented and measured.