When we consider user's convenience for electronic transactions, it might be desirable to generate a digital signature using biometrics. However, it is not easy nor practicable in today's communications environment because of inaccurate measuring and potential hill-climbing attacks with regard to biometrics, unless specific hardware storage is provided for manipulating signature keys or biometric templates securely. In this paper, we study a simple practical method for biometrics based digital signature generation without such restriction. It is based on the existing tools in software in our proposed model where a general digital signature such as RSA can be applied without losing its security. This is not a cryptography paper but rather written from the practical perspectives.

This paper proposes a suboptimal algorithm for the maximum likelihood detection (MLD) in multiple-input multiple-output (MIMO) communications. The proposed algorithm regards transmitted signals as continuous variables in the same way as a common method for the discrete optimization problem, and then searches for candidates of the transmitted signals in the direction of a modified gradient vector of the metric. The vector is almost proportional to the direction of the noise enhancement, from which zero-forcing (ZF) or minimum mean square error (MMSE) algorithms suffer. This method sets the initial guess to the solution by ZF or MMSE algorithms, which can be recursively calculated. Also, the proposed algorithm has the same complexity order as that of conventional suboptimal algorithms. Computer simulations demonstrate that it is much superior in BER performance to the conventional ones.

Long-period gratings (LPGs) are written in the fibers un-preheated and preheated. The influence of residual stress on trimming resonance wavelengths by heating the LPGs is investigated comparing the post-heating changes of the transmission characteristics. It becomes evident that the residual stress relaxation shifts resonance wavelengths to shorter wavelengths quickly and the glass structure modification moves them to longer wavelengths slowly. The relaxation rate of the glass structure drops rapidly with the decrease in heating temperature, and the influence of the residual stress relaxation appears more strongly at the early stage of heating at a lower temperature. The trimming wavelength range can be broadened on the short wavelength side by decreasing the heating temperature. We could adjust resonance wavelengths without significant peak loss changes by the residual stress relaxation before writing LPGs, though the trimming range becomes narrow.

MIMO systems using a space division multiplexing (SDM) technique in which each transmit antenna sends an independent signal substream have been studied as one of the successful applications to increase data rates in wireless communications. The throughput of a MIMO channel can be maximized by using an eigenbeam-SDM (E-SDM) technique, and this paper investigates the practical performance of 22 and 44 MIMO E-SDM based on indoor measurements. The channel capacity and bit error rate obtained in various uniform linear array configurations are evaluated and are compared with the corresponding values for conventional SDM. Analysis results show that the bit error rate performance of E-SDM is better than that of SDM and that E-SDM gives better performance in line-of-sight (LOS) conditions than in non-LOS ones. They also show that the performance of E-SDM in LOS conditions depends very much on the array configuration.

To improve the channel estimation accuracy of multiple-input multiple-output (MIMO) multiplexing, we previously proposed iterative QR-decomposition with M-algorithm (QRD-M) with decision directed channel estimation. In this paper, to keep the computational complexity low while further improving the transmission performance, we will modify previously proposed iterative QRD-M by incorporating cyclic redundancy check (CRC) coding. In the proposed method, transmitted signals are ranked according to their results of CRC decoding and the received signal-to-interference plus noise power ratio (SINR). In the modified M-algorithm, since the results of Turbo decoding and CRC decoding are used to generate the surviving symbol replica, the accuracy of signal detection in the following steps can be improved. Furthermore, based on the results of CRC decoding, iterative process can be terminated before reaching the maximum allowable number of iterations. Computer simulation results show that the loss in the required average received signal energy per bit-to-noise power spectrum density ratio Eb/N0 for average packet error rate (PER) = 10-2 is only about 0.4 dB from maximum likelihood detection (Full MLD) with ideal channel estimation.

A new digital calibration scheme for a 14 bit binary weighted current-steering digital-to-analog converter (DAC) is presented. This scheme uses a simple current comparator for the current measurement instead of a high-resolution ADC. Therefore, a faster calibration cycle and smaller additional circuits are possible compared to the scheme with the high-resolution ADC. In the proposed calibration scheme, the lowest 8 bit part of the DAC is used for both error correction and normal operation. Therefore, the extra DACs required for calibration are only a 3 bit DAC and a 6 bit DAC. Nevertheless, a large calibration range is achieved. Full 14 bit resolution is achieved with a small chip-area. The simulation results show that DNL and INL after calibration are 0.26 LSB and 0.46 LSB, respectively. They also show that the spurious free dynamic range is 83 dB (57 dB) for signals of 24 kHz (98 MHz) at 200 Msps update rate.

A new radio-frequency (RF) radiated immunity/susceptibility test method using four-septum TEM cell is proposed. A rotating-EM field can be generated inside the cell by feeding four-different RF DSB-SC signals to four septa arranged in the cell. Since a polarization plane of the rotating-EM field rotates in a low speed, the immunity/susceptibility test for the EM field with various polarizations can be conducted more easily. In this paper, a technique for generating the rotating-EM field in the cell is investigated. The basic characteristics of the cell and the rotating-EM field by using the technique are clarified. To verify the validity of this test method, a RF radiated susceptibility of a printed circuit board is measured. The measured results are verified by comparing with the theoretical results based on modified telegrapher's equations.

In this paper, we propose tight performance upper bounds for convolutional codes terminated with an input sequence of finite length. To obtain the upper bounds, a generalized weight enumerator of single error event is defined to represent the relation between the Hamming distance of the coded output and the Hamming distance of the selected input bits of a terminated convolutional code. In the generalized weight enumerator of single error event, codewords composed of multiple error events are not counted to provide tighter performance upper bounds. The upper bounds on frame error rate (FER) and average bit error rate (BER) of selected bits are computed from the generalized weight enumerators of single error event. A simple method is presented to compute the weight enumerator of a terminated convolutional code based on a modified trellis diagram.

This paper proposes effective energy feature normalization methods for robust speech recognition in noisy environments. We first develop an energy subtraction method and a modified method for the Log-energy Dynamic Range Normalization (ERN) using inverse function. We then present the hybrid method combining the energy subtraction and the modified ERN. Using Aurora2.0 database for representative evaluations, a significant performance improvement over the ERN method is demonstrated.

A carrier frequency synchronization scheme is proposed for orthogonal frequency-division multiplexing (OFDM) systems in the presence of phase noise (PHN). In the proposed scheme, carrier frequency synchronization is performed based on the maximum-likelihood (ML) algorithm using an OFDM preamble symbol. The proposed scheme is compared with conventional methods. Simulation results are presented to illustrate the effectiveness of the proposed scheme in the presence of PHN.

It is an innovative idea for modern PLL generation to control the bandwidth proportionally to the reference frequency. Recently, a frequency of the operating clock in microprocessors has been required to be changed frequently and widely in order to manage power consumption and throughput. A new compact switched capacitor (SC) filter which has fully flat response has been developed for adaptive biased PLLs. We have also developed a new digital control method for achieving the wider frequency range. The measured performances of the test chip were good enough for the use in the microprocessors.

This paper presents a new Fuzzy Logic Controller (FLC) having the ability to support rational-powered membership functions. These functions are extended forms of triangular/trapezoidal membership functions, and also those functions which are generated by applying linguistic hedges. A two-input, single-output, nine-rule Takagi-Sugeno-Kang (TSK) type FLC is designed in 0.35 µm standard CMOS technology. This controller can also be used as a standard (Mamdani) type FLC having singleton output membership functions, as well as a Linguistic Hedge FLC (LHFLC). Mixed analog/digital realization of the circuit makes the design programmable and extendable, while having relatively low power consumption. Current mode realization of the circuits leads to simple and intuitive configurations. For a particular set of programming parameters, simulation results of the controller using HSPICE simulator and level 49 parameters (BSIM3v3), show an average power consumption of 5 mW, and an RMS error of 1.32% compared to ideal results obtained from MATLAB software.

This paper proposes a design technique to reduce the power dissipation of CML driver for on-chip transmission-lines. CML drivers can operate at higher frequency than conventional static CMOS logic drivers. On the other hand, the power dissipation is larger than that of CMOS static logic drivers. The proposed method reduces the power dissipation by using an impedance-unmatched driver instead of the conventional impedance-matched driver. Measurement results show that the proposed method reduces the power dissipation by 32% compared with a conventional design at 12.5 Gbps.

In recent years, network analysis has revealed that some real networks have the properties of small-world and/or scale-free networks. In this study, a simple Genetic Algorithm (GA) is regarded as a network where each node and each edge respectively represent a population and the possibility of the transition between two nodes. The characteristic path length (CPL), which is one of the most popular criteria in small-world networks, is derived analytically and shows how much the crossover operation affects the path length between two populations. As a result, the crossover operation is not so useful for shortening the CPL.

In this paper, we present a directional interpolation filter in which the minimum and maximum pixels in the given window are excluded. Image pixels within a predefined window are ranked and classified as minimum-maximum or exclusive level, and then passed through the interpolation and identity filters, respectively. Extensive simulations show that the proposed filter performs better than other nonlinear filters in preserving desired image features while reducing impulse noise effectively.

For a digitally controlled phase-locked loop (PLL), we evaluate the use of a clock-period comparator (CPC). In this PLL, only the frequency lock operation should be performed; however, the phase lock operation is also simultaneously achieved by performing the clock-period comparison when the phases of the reference signal and the output signal approach each other. Theoretically a lock-up operation was conducted. In addition, we succeeded in digitizing a voltage controlled oscillator (VCO) with a linear characteristic. We confirmed a phase lock operation with a slight loop characteristic through SPICE simulation.

In this paper, we discuss the effects of switch resistances on the step response of switched-capacitor (SC) circuits, especially multiplying digital-to-analog converters (MDACs) in pipelined analog-to-digital converters. Theory and simulation results reveal that the settling time of MDACs can be decreased by optimizing the switch resistances. This switch resistance optimization does not only effectively increase the speed of single-bit MDACs, but also of multi-bit MDACs. Moreover, multi-bit MDACs are faster than the single-bit MDACs when slewing occurs during the step response. With such an optimization, the response of the switch will be improved by up to 50%.

An 8.8-GS/s 6-bit CMOS analog-to-digital converter (ADC) chip was implemented by time-interleaving eight 1.1-GS/s 6-bit flash ADCs with a 0.18-µm CMOS process. Eight uniformly-spaced 1.1 GHz clocks with 50% duty cycle for the eight flash ADCs were generated by a clock generator, which consists of a phase-locked-loop, digital phase adjusters and digital duty cycle correctors. The input bandwidth of ADC with the ENOB larger than 5.0 bits was measured to be 1.2 GHz. The chip area and power consumption were 2.24 mm2 and 1.6 W, respectively.

In this paper we modeled and analyzed the ridge type InGaAlAs/InP semiconductor laser with lateral current confinement structure, and optimized the design for the ridge wave guide with the current confinement. We proposed and fabricated the ridge type InGaAlAs/InP laser with a cost effective selective undercut etching method and demonstrated the improvement of the ridge laser performance. This paper provides a solution to solve the cost/yield issue for conventional BH (buried hetero-structure) type laser and performance issue for conventional ridge type laser.

A novel asymmetric MOSFET with no LDD on the source side is simulated on bulk-Si using a device simulator (SILVACO). In order to overcome the problems of the conventional asymmetric process, a novel asymmetric MOSFET using mesa structure and sidewall spacer gate is proposed which provides self-alignment process, aggressive scaling, and uniformity. First of all, we have simulated to compare the characteristics between asymmetric and symmetric MOSFETs. Basically, both asymmetric and symmetric MOSFETs have an n-type channel (25-nm) and the same physical parameters. When we compare this with the 25-nm symmetric MOSFET, the proposed asymmetric MOSFET shows better device performances.