An efficient clustering strategy for estimation of distribution algorithms (EDAs) is presented. It is used for properly fitting probabilistic models that play an important role in guiding search direction. To this end, a fitness-aided ordering scheme is devised for deciding the input sequence of samples (i.e., individuals) for clustering. It can effectively categorise the individuals by using the (available) information about fitness landscape. Moreover, a virtual leader is introduced for providing a reliable reference for measuring the distance from samples to its own cluster. The proposed algorithm incorporates them within the framework of random the leader algorithm (RLA). Experimental results demonstrate that the proposed approach is more effective than the existing ones with regard to probabilistic model fitting.

In this study, we propose a new acoustic model including the human ear canal and a thin tube earphone. The use of a tube earphone enables simultaneous listening of both virtual and real surrounding sound. First, we perform acoustic FDTD (finite difference time domain) simulations using an MRI head model with ear canals. The calculated external impedance viewed from the eardrum numerically shows that the influence of the inserted tube is small. A listening experiment with six subjects also confirms the effectiveness of a tube earphone. Second, we calculate HRTFs (head-related transfer functions) for eight directions in the horizontal plane to realize sound localization with a tube earphone. We also design inverse filters based on the propagation calculations including the characteristics of tube earphones. Finally we evaluate the localization system by another listening experiment with six subjects. The results reveal that the applicability of a system with tube earphones and inverse filters, particularly for the front directions.

Floating dummy metal fills inserted for planarization of multi-dielectric layers have created serious problems because of increased interconnect capacitance and the enormous number of fills. We present new dummy filling methods to reduce the interconnect capacitance and the number of dummy metal fills needed. These techniques include three ways of filling: 1) improved floating square fills, 2) floating parallel lines, and 3) floating perpendicular lines (with spacing between dummy metal fills above and below signal lines). We also present efficient formulas for estimating the appropriate spacing and number of fills. In our experiments, the capacitance increase using the conventional regular square method was 13.1%, while that using the methods of improved square fills, extended parallel lines, and perpendicular lines were 2.7%, 2.4%, and 1.0%, respectively. Moreover, the number of necessary dummy metal fills can be reduced by two orders of magnitude through use of the parallel line method.

In this paper, we propose a new software reliability growth model which is the mixture of two exponential reliability growth models, one of which has the reliability growth and the other one does not have the reliability growth after the software is released upon completion of testing phase. The mixture of two such models is characterized by a weighted factor p, which is the proportion of reliability growth part within the model. Firstly, this paper discusses an optimal software release problem with regard to the expected total software cost incurred during the warranty period under the proposed software reliability growth model, which generalizes Kimura, Toyota and Yamada's (1999) model with consideration of the weighted factor. The second main purpose of this paper is to apply the Bayesian approach to the optimal software release policy by assuming the prior distributions for the unknown parameters contained in the proposed software reliability growth model. Some numerical examples are presented for the purpose of comparing the optimal software release policies depending on the choice of parameters by the non-Bayesian and Bayesian methods.

This paper presents a standard cell-based frequency synthesizer with dynamic frequency counting (DFC) for multiplying input reference frequency by N times. The dynamic frequency counting loop uses variable time period to estimate and tune the frequency of digitally-controlled oscillator (DCO) which enhances frequency detection's resolution and loop stability. Two ripple counters serve as frequency estimator. Conventional phase-frequency detector (PFD) thus is replaced with a digital arithmetic comparator to yield a divider-free circuit structure. Additionally, a 15 bits DCO with the least significant bit (LSB) resolution 1.55 ps is designed by using the gate capacitance difference of 2-input NOR gate in fine-tuning stage. A modified incremental data weighted averaging (IDWA) circuit is also designed to achieve improved linearity of DCO by dynamic element matching (DEM) skill. Based on the proposed standard cell-based frequency synthesizer, a test chip is designed and verified on 0.35-µm complementary metal oxide silicon (CMOS) process, and has a frequency range of (18-214) MHz at 3.3 V with peak-to-peak (Pk-Pk) jitter of less than 70 ps at 192 MHz/3.3 V.

A high quality-factor of active inductor has been implemented by using the 0.18 µm 1P6M CMOS technologies in this work. By adding a feedback resistance and a regulated gain stage transistor into the conventional cascade-grounded approach, the quality-factor and performance of CMOS active inductor can be improved. This novel active inductor demonstrated a maximum quality-factor of 540 and a 3.2 nH inductance at 4.3 GHz, where the self-resonant frequency was 5.4 GHz. An active CMOS bandpass filter was also fabricated including this tunable high quality factor active inductor, performing an insertion loss of 0.2 dB and a return loss more than 32 dB with a tuning range from 3.45 GHz to 3.6 GHz. The input IP3 was -2.4 dBm, and the noise figure was 14.1 dB with a 28 mW dc power consumption.

This paper shows a design method for a sequential circuit by using a Look-Up Table (LUT) ring. The method consists of two steps: The first step partitions the outputs into groups. The second step realizes them by LUT cascades, and allocates the cells of the cascades into the memory. The system automatically finds a fast implementation by maximally utilizing available memory. With the presented algorithm, we can easily design sequential circuits satisfying given specifications. The paper also compares the LUT ring with logic simulator to realize sequential circuits: the LUT ring is 25 to 237 times faster than a logic simulator that uses the same amount of memory.

The Reed-Solomon code is a versatile channel code pervasively used for communication and storage systems. The bit-serial Reed-Solomon encoder has a simple structure, although it is somewhat difficult to understand the algorithm without considerable theoretical background. Some professionals and students, not able to understand the algorithm thoroughly, might need to implement the bit-serial encoder for themselves. In this letter, a step-by-step method is presented for the implementation of the bit-serial encoder even without understanding the internal algorithm, which would be helpful for VHDL, DSP, and simulation programming.

This work presents a frequency-scaling low-power (FSLP) design methodology for managing power consumption of cores in the tile-based network-on-chip (NOC) architecture. A moving picture experts group (MPEG) core is tested using the field-programmable gate array (FPGA) implementation to verify the feasibility of the proposed method. Measurement results show that about 30% power consumption can be saved in the MPEG core and reveal that the proposed FSLP design method can be suitable for cores in the tile-based NOC applications.

This paper presents a processor architecture for high-speed and reliable stereo matching based on adaptive window-size control of SAD (Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using images divided into non-overlapping regions, and the matching result is iteratively refined by reducing a window size. Window-parallel-and-pixel-parallel architecture is also proposed to achieve to fully exploit the potential parallelism of the algorithm. The architecture also reduces the complexity of an interconnection network between memory and functional units based on the regularity of reference pixels. The stereo matching processor is implemented on an FPGA. Its performance is 80 times higher than that of a microprocessor (Pentium4@2 GHz), and is enough to generate a 3-D depth image at the video rate of 33 MHz.

This paper proposes a genetically inspired adaptive clustering algorithm for numerical and categorical data sets. To this end, unique encoding method and fitness functions are developed. The algorithm automatically discovers the actual number of clusters and efficiently performs clustering without unduly compromising cluster-purity. Moreover, it outperforms existing clustering algorithms.

In this paper, an efficient equivalence checking method for two C descriptions is described. The equivalence of two C descriptions is proved by symbolic simulation. Symbolic simulation used in this paper can prove the equivalence of all of the variables in the descriptions. However, it takes long time to verify the equivalence of all of the variables if large descriptions are given. Therefore, in order to improve the verification, our method identifies textual differences between descriptions. The identified textual differences are used to reduce the number of equivalence checkings among variables. The proposed method has been implemented in C language and evaluated with several C descriptions.

This paper tackles the problem of detecting a random signal embedded in additive white noise. Although the likelihood ratio test (LRT) is the well-known optimum detector for this problem, it may not be easily realized in applications such as radar, sonar, seismic, digital communications, speech analysis and automatic fault detection in machinery, for which suboptimal quadratic detectors have been extensively employed. In this paper, the relationships between four suboptimal quadratic detection schemes, namely, the energy, matched subspace, maximum deflection ratio as well as spectrum matching detectors, and the LRT are studied. In particular, we show that each of those suboptimal detectors can approach the optimal LRT under certain operating conditions. These results are verified via Monte Carlo simulations.

In conventional OFDM systems, the effect of inter-block-interference (IBI) can be completely removed by inserting sufficient redundant symbols between successive transmission blocks. In this paper, based on the reformulated received block symbols of the discrete multirate filterbanks model, a new transceiver model for the cyclic prefix (CP) OFDM systems is proposed, associated with the oblique projector technique (view as the pre-processor for achieving IBI-free). Consequently, a novel ISI-free receiver with the zero-order FIR zero-forcing (ZF) filterbanks equalizer can be devised, under noise-free environment. For performance comparison the bit-error-rate (BER) is investigated for the cases of noisy and noise-free channels. In all cases, viz., the length of CP is shorter or longer than the order of the channel impulse response, we show that the same BER performance compared with the one suggested in [3] can be achieved, under the same assumptions and conditions. Since a simple cascade configuration of the IBI cancellation using the oblique projector followed by the ISI cancellation using the zero-order FIR ZF filterbanks equalizer can be realized for OFDM systems with sufficient or insufficient CP, the complexity of transceiver design can be reduced.

Locality in high frequency diffraction is embodied in the Method of Moments (MoM) in view of the method of stationary phase. Local-domain basis functions accompanied with the phase detour, which are not entire domain but are much larger than the segment length in the usual MoM, are newly introduced to enhance the cancellation of mutual coupling over the local-domain; the off-diagonal elements in resultant reaction matrix evanesce rapidly. The Fresnel zone threshold is proposed for simple and effective truncation of the matrix into the sparse band matrix. Numerical examples for the 2-D strip and the 2-D corner reflector demonstrate the feasibility as well as difficulties of the concept; the way mitigating computational load of the MoM in high frequency problems is suggested.

In this paper we propose a novel and efficient method for the optimization of the power/ground (P/G) network in VLSI circuit layouts with reliability constraints. Previous algorithms in the P/G network sizing used the sequence-of-linear-programming (SLP) algorithm to solve the nonlinear optimization problems. However the transformation from nonlinear network to linear subnetwork is not optimal enough. Our new method is inspired by the biological evolution and use the grid-genetic-algorithm (GGA) to solve the optimization problem. Experimental results show that new P/G network sizes are smaller than previous algorithms, as the fittest survival in the nature. Another significant advance is that GGA method can be applied for all P/G network problems because it can get the results directly no matter whether these problems are linear or not. Thus GGA can be adopted in the transient behavior of the P/G network sizing in the future, which recently faces on the obstacles in the solution of the complex nonlinear problems.

Design of portable battery operated multimedia devices requires energy-efficient multiplication circuits. This paper proposes a novel architectural technique to reduce power consumption of digital multipliers. Unlike related approaches which focus on multiplier transition activity reduction, we concentrate on dynamic reduction of supply voltage. Two implementation schemes capable of dynamically adjusting a double voltage supply to input data variation are presented. Simulations show that using these schemes we can reduce energy consumption of 1616-bit multiplier by 34% and 29% on peak and by 10% and 7% on average with area overhead of 15% and 4%, respectively, while maintaining the performance of traditional multiplier.

In order to eliminate the co-channel and multi-path interference of quasi-synchronous code division multiple access (QS-CDMA) systems, spreading sequences with low or zero correlation zone (LCZ or ZCZ) can be used. The significance of LCZ/ZCZ to QS-CDMA systems is that, even there are relative delays between the transmitted spreading sequences due to the inaccurate access synchronization and the multipath propagation, the orthogonality (or quasi-orthogonality) between the transmitted signals can still be maintained, as long as the relative delay does not exceed certain limit. In this paper, several lower bounds on the aperiodic autocorrelation and crosscorrelation of binary LCZ/ZCZ sequence set with respect to the family size, sequence length and the aperiodic low or zero correlation zone, are derived. The results show that the new bounds are tighter than previous bounds for the LCZ/ZCZ sequences.

In this letter, new results on the BER performance of multitone DS-CDMA systems for transmissions over Nakagami-m fading channels with exponentially decaying multipath intensity profile are presented. The results show that, in viewpoint of the BER performance, there is a critical relation between the number of resolvable paths and the effect of the rate of average power decay.

An efficient void filling (VF) algorithm is proposed for wavelength division multiplexing (WDM) optical packet switches (OPSes) handling variable-packet-length self-similar traffic. The computation complexity of the proposed algorithm is extremely low. We further compare the switching performance of the proposed algorithm with that of the conventional one. We demonstrate that the proposed algorithm offers significantly lower computation complexity with adequate performance.