A new dual-slope ramp (DSR) reset waveform is proposed to improve the dark room contrast ratio in AC-PDPs. The proposed reset waveform has two different voltage slopes during a ramp-up period. The first voltage slope lower than the conventional ramp voltage slope plays a role in producing the priming particles under the low background luminance, which is considered to be a kind of pre-reset discharge. On the other hand, the second voltage slope higher than the conventional ramp voltage slope produces a stable reset discharge due to the presence of the priming particles, but gives rise to a slight increase in the background luminance. Thus, a bias voltage is also applied during a part of the second voltage-slope period to adjust the background luminance and address discharge characteristics. As a result, the proposed dual-slope reset waveform can lower the background luminance without causing the discharge instability, thereby improving the high dark room contrast ratio of an AC-PDP without reducing the address voltage margin.

The relative permittivity and permeability are discontinuous at the grating profile, and the electric and magnetic flux densities are continuous. As for the method of analysis for scattering waves by surface relief gratings placed in conical mounting, the spatial harmonic expansion approach of the flux densities are formulated in detail and the validity of the approach is shown numerically. The present method is effective for uniform regions such as air and substrate in addition to grating layer. The matrix formulations are introduced by using numerical calculations of the matrix eigenvalue problem in the grating region and analytical solutions separated for TE and TM waves in the uniform region are described. Some numerical examples for linearly and circularly polarized incidence show the usefulness of the flux densities expansion approach.

An inverse scattering problem of estimating the surface impedance for an inhomogeneous half-space is investigated. By virtue of the fact that the far field representation contains the spectral function of the scattered field, complex values of the function are estimated from a set of absolute values of the far field. An approximate function for the spectral function is reconstructed from the estimated complex values by the least-squares sense. The surface impedance is estimated through calculating the field on the surface of the half-space expressed by the inverse Fourier transform. Numerical examples are given and the accuracy of the estimation is discussed.

Waveguide-type optical amplifiers doped with Ytterbium and Erbium ions are theoretically studied. Sensitization of Er-doped amplifiers with Yb ion doping have many advantages such as the possibility of using broader pumping wavelength range and efficient pumping with smaller pumping power. Transient amplification characteristics of optical short pulses are numerically analyzed using FDTD method. The amplification characteristics are compared with the result of the steady state analysis using the rate equations.

By inserting a slot and metallic strips at the widened stub in a single layer and fed by coplanar waveguide (CPW) transmission line, novel dual-band and broadband operations are presented. The proposed antennas are designed to have dual-band operation suitable for applications in DCS (1720-1880 MHz), PCS (1850-1990 MHz), IMT-2000 (1920-2170 MHz), and IEEE 802.11 WLAN standards in the 2.4 GHz (2400-2484 MHz) and 5.2 GHz (5150-5350 MHz) bands. The dual-band antennas are simple in design, and the two operating modes of the proposed antennas are associated with perimeter of slots and loading metallic strips, in which the lower operating band can be controlled by varying the perimeters of the outer square slot and the higher band depend on the inner slot of the widened stub. The experimental results of the proposed antennas show the impedance bandwidths of the two operating bands, determined from 10-dB return loss, larger than 61% and 27% of the center frequencies, respectively.

This paper concerns a new model for estimating the wire length distribution (WLD) of a system-on-a-chip (SoC). The WLD represents the correlation between wire length and the number of interconnects, and we can predict circuit performances such as power consumption, maximum clock frequency, and chip size from the WLD. A WLD model considering core utilization has been proposed, and the core utilization has a large impact on circuit performance. However, the WLD model can treat only a one-function circuit. We propose a new WLD model considering core utilization to estimate the wire length distribution of SoC, which consists of several different-function macroblocks. We present an optimization method to determine each core utilization of macroblocks.

Incremental modification and optimization in VLSI physical design is of fundamental importance. Based on the O-tree (ordered tree) representation which has more prominent advantages in comparison with other topological representations of non-slicing floorplans, in this paper, we present an incremental placement algorithm for BBL (Building Block Layout) design in VLSI physical design. The good performance of experimental results in dealing with some instances proves the effectiveness of our algorithm.

To achieve both of a high peak performance and low average power characteristics, frequency-voltage cooperative control processor has been proposed. The processor schedules its operating frequency according to the required computation power. Its operating voltage or body bias voltage is adequately modulated simultaneously to effectively cut down either switching current or leakage current, and it results in reduction of total power dissipation of the processor. Since a frequency-voltage cooperative control processor has two or more operating frequencies, there are countless scheduling methods exist to realize a certain number of cycles by deadline time. This proposition is frequently appears in a hard real-time system. This paper proves two important theorems, which give the power-minimum frequency scheduling method for any types of frequency-voltage cooperative control processor, such as Vdd-control type, Vth-control type and Vdd-Vth-control type processors.

In deep submicron designs, predicting gate slews and delays for interconnect loads is vitally important for Static Timing Analysis (STA). The effective capacitance Ceff concept is usually used to calculate the gate delay of interconnect loads. Many Ceff algorithms have been proposed to compute gate delay of interconnect loads. However, less work has been done to develop a Ceff algorithm which can accurately predict gate slew. In this paper, we propose a novel method for calculating the Ceff of interconnect load for gate slew. We firstly establish a new expression for Ceff in 0.8Vdd point. Then the Integration Approximation method is used to calculate the value of Ceff in 0.8Vdd point. In this method, the integration of a complicated nonlinear gate output is approximated with that of a piecewise linear waveform. Based on the value of Ceff in 0.8Vdd point, Ceff of interconnect load for gate slew is obtained. The simulation results demonstrate a significant improvement in accuracy.

Interconnect Length Distribution (ILD) represents the correlation between the number of interconnects and their length. The ILD can predict power consumption, clock frequency, chip size, etc. High core utilization and small circuit area have been reported to improve chip performance. We propose an ILD model to predict the correlation between core utilization and chip performance. The proposed model predicts the influences of interconnect length and interconnect density on circuit performances. As core utilization increases, small and simple circuits improve the performances. In large complex circuits, decreasing the wire coupling capacitance is more important than decreasing the total interconnect length for improvement of chip performance. The proposed ILD model expresses the actual ILD more accurately than conventional models.

Simple closed-form expressions for efficiently calculating on-chip interconnect capacitances are presented. The formulas are expressed with second-order polynomial functions which do not include exponential functions. The runtime of the proposed formulas is about 2-10 times faster than those of existing formulas. The root mean square (RMS) errors of the proposed formulas are within 1.5%, 1.3%, 3.1%, and 4.6% of the results obtained by a field solver for structures with one line above a ground plane, one line between ground planes, three lines above a ground plane, and three lines between ground planes, respectively. The proposed formulas are also superior in accuracy to existing formulas.

In this paper, we propose a new Interconnect Length Distribution (ILD) model to evaluate X architecture. X architecture uses 45-wire orientations in addition to 90-wire orientations, which contributes to reduce the total wire length and the number of vias. In this paper, we evaluated interconnect length distribution of diagonal (45orientations) and all-directional wiring. The average length and the longest length of interconnect are estimated, and 18% reduction in power consumption and 17% improvement in clock frequency can be obtained by the diagonal wiring in the experimental results. The all-directional wiring does not have large advantage as compared the diagonal wiring.

In this paper, we propose a new software reliability growth model which is the mixture of two exponential reliability growth models, one of which has the reliability growth and the other one does not have the reliability growth after the software is released upon completion of testing phase. The mixture of two such models is characterized by a weighted factor p, which is the proportion of reliability growth part within the model. Firstly, this paper discusses an optimal software release problem with regard to the expected total software cost incurred during the warranty period under the proposed software reliability growth model, which generalizes Kimura, Toyota and Yamada's (1999) model with consideration of the weighted factor. The second main purpose of this paper is to apply the Bayesian approach to the optimal software release policy by assuming the prior distributions for the unknown parameters contained in the proposed software reliability growth model. Some numerical examples are presented for the purpose of comparing the optimal software release policies depending on the choice of parameters by the non-Bayesian and Bayesian methods.

In order to eliminate the co-channel and multi-path interference of quasi-synchronous code division multiple access (QS-CDMA) systems, spreading sequences with low or zero correlation zone (LCZ or ZCZ) can be used. The significance of LCZ/ZCZ to QS-CDMA systems is that, even there are relative delays between the transmitted spreading sequences due to the inaccurate access synchronization and the multipath propagation, the orthogonality (or quasi-orthogonality) between the transmitted signals can still be maintained, as long as the relative delay does not exceed certain limit. In this paper, several lower bounds on the aperiodic autocorrelation and crosscorrelation of binary LCZ/ZCZ sequence set with respect to the family size, sequence length and the aperiodic low or zero correlation zone, are derived. The results show that the new bounds are tighter than previous bounds for the LCZ/ZCZ sequences.

There are several optimization techniques available for improving rendering speed of direct volume rendering. An acceleration method using the hierarchical min-max map requires little preprocessing and data storage while preserving image quality. However, this method introduces computational overhead because of unnecessary comparison and level shift between blocks. In this paper, we propose an efficient space-leaping method using optimal-sized blocks. To determine the size of blocks, our method partitions an image plane into several uniform grids and computes the minimum and the maximum depth values for each grid. We acquire optimal block sets suitable for individual rays from these values. Experimental results show that our method reduces rendering time when compared with the previous min-max octree method.

The IEEE 802.11 distributed coordination function (DCF) provides a contention-based distribution channel access mechanism for stations to share the wireless medium. However, performance of the DCF drops dramatically in terms of throughput, delay and jitter as the number of active stations becomes large. In this paper, we propose a simple and effective scheme, called distributed coordination function with virtual group (DCF/VG), for improving the performance of the IEEE 802.11 DCF mechanism. In this scheme, each station independently decides a virtual group cycle taking into account the current contention level. The virtual group cycle consists of one or more virtual groups and a virtual group includes an idle and a busy period. Each station chooses one virtual group and operates only in the chosen group of the cycle. In other words, each station decreases its backoff counter and tries to transmit its packet during the period of the chosen virtual group like in the IEEE 802.11 DCF. Performance of the proposed scheme is investigated by numerical analysis and simulation. Our results show that the proposed scheme is very effective and has high throughput and low delay and jitter behaviors under a wide range of contention levels.

In this paper we propose a novel and efficient method for the optimization of the power/ground (P/G) network in VLSI circuit layouts with reliability constraints. Previous algorithms in the P/G network sizing used the sequence-of-linear-programming (SLP) algorithm to solve the nonlinear optimization problems. However the transformation from nonlinear network to linear subnetwork is not optimal enough. Our new method is inspired by the biological evolution and use the grid-genetic-algorithm (GGA) to solve the optimization problem. Experimental results show that new P/G network sizes are smaller than previous algorithms, as the fittest survival in the nature. Another significant advance is that GGA method can be applied for all P/G network problems because it can get the results directly no matter whether these problems are linear or not. Thus GGA can be adopted in the transient behavior of the P/G network sizing in the future, which recently faces on the obstacles in the solution of the complex nonlinear problems.

Design of portable battery operated multimedia devices requires energy-efficient multiplication circuits. This paper proposes a novel architectural technique to reduce power consumption of digital multipliers. Unlike related approaches which focus on multiplier transition activity reduction, we concentrate on dynamic reduction of supply voltage. Two implementation schemes capable of dynamically adjusting a double voltage supply to input data variation are presented. Simulations show that using these schemes we can reduce energy consumption of 1616-bit multiplier by 34% and 29% on peak and by 10% and 7% on average with area overhead of 15% and 4%, respectively, while maintaining the performance of traditional multiplier.

This work presents a frequency-scaling low-power (FSLP) design methodology for managing power consumption of cores in the tile-based network-on-chip (NOC) architecture. A moving picture experts group (MPEG) core is tested using the field-programmable gate array (FPGA) implementation to verify the feasibility of the proposed method. Measurement results show that about 30% power consumption can be saved in the MPEG core and reveal that the proposed FSLP design method can be suitable for cores in the tile-based NOC applications.

Sinusoidal representation has been widely applied to speech modification, low bit rate speech and audio coding. Usually, speech signal is analyzed and synthesized using the overlap-add algorithm or the peak-picking algorithm. But the overlap-add algorithm is well known for high computational complexity and the peak-picking algorithm cannot track the transient and syllabic variation well. In this letter, both algorithms are applied to speech analysis/synthesis. Peaks are picked in the curve of power spectral density for speech signal; the frequencies corresponding to these peaks are arranged according to the descending orders of their corresponding power spectral densities. These frequencies are regarded as the candidate frequencies to determine the corresponding amplitudes and initial phases according to the least mean square error criterion. The summation of the extracted sinusoidal components is used to successively approach the original speech signal. The results show that the proposed algorithm can track the transient and syllabic variation and can attain the good synthesized speech signal with low computational complexity.