Recent developments and case studies regarding VLSI device chip failure analysis are reviewed. The key failure analysis techniques reviewed include EMMS (emission microscopy), OBIC (optical beam induced current), LCM (liquid crystal method), EBP (electron beam probing), and FIB (focused ion beam method). Further, future possibilities in failure analysis, and some promising new tools are introduced.

This letter extends the Yule-Walker method to the estimation of ARMA parameters from output measurements corrupted by noise. In the proposed method it is assumed that the noise variance and the input are unknown. An algorithm for the estimation of noise variance is, therefore, given. The use of the variance estimation method proposed here together with the Yule-Walker equations allow the estimation of the parameters of a minimum phase ARMA model based only on noisy measurements of its output. Moreover, using this method it is not necessary to slove a set of nonlinear equations for MA parameter estimation as required in the conventional correlation based methods.

This paper advocates the use of linear objective function in analytic analog placement. The role of linear and quadratic objctive functions in the behavior and results of an analog placement algorithm based on the force directed method is discussed. Experimental results for a MCNC benchmark circuit and another one from text books are shown to demonstrate the effect of a linear and a quadratic objective function on the analog constraint satisfaction and CPU time. By introducing linear objective function to the algorithm, we obtain better placements in terms of analog constraint satisfaction and computation cost than in case of conventional quadratic objective function.

This paper describes a 32-bit fully asynchronous microprocessor, with 4-stage pipeline based on a RISC-like architecture. Issues relevant to the processor such as design of self-timed datapath, asynchronous controller and interconnection circuits are discussed. Simulation results are included using parameters extracted from layout, which showed about the 300 MIPS processing speed and used 71,000 transistors with 0.5 µm CMOS technology.

In this paper, a middle-mapping learning algorithm for cellular associative memories is presented. This algorithm makes full use of the properties of the cellular neural network so that the associative memory has some advantages compared with the memory designed by the ourter product method. It can guarantee each prototype is stored at an equilibrium point. In the practical implementation, it is easy to build up the circuit because the weight matrix presenting the connection between cells is not symmetric. The synchronous updating rule makes its associative speed very fast compared to the Hopfield associative memory.

A novel pulse neural network model for sound localization has been proposed. Our model is based on the physiological auditory nervous system. Human beings can perceive the sound direction using inter-aural time difference (ILD) and inter-aural level difference (ILD) of two sounds. The model extracts these features using only pulse train information. The model is divided roughly into three sections: preprocessing for input signals; transforming continuous signals to pulse trains; and extracting features. The last section consists of two parts: ITD extractor and ILD extractor. Both extractors are implemented using a pulse neuron model. They have the same network structure, differing only in terms of parameters and arrangements of the pulse neuron model. The pulse neuron model receives pulse trains and outputs a pulse train. Because the pulses have only simple informations, their data structures are very simple and clear. Thus, a strict design is not required for the implementation of the model. These advantages are profitable for realizing this model by hardware. A computer simulation has demonstrated that time and level differences between two signals have been successfully extracted by the model.

We have aimed at constructing a forward dynamics model (FDM) of the human arm in the form of an artificial neural network while recordings of EMG and movement trajectories. We succeeded in: (1) estimating the joint torques under isometric conditions and (2) estimating trajectories from surface EMG signals in the horizontal plane. The human arm has seven degrees of freedom: the shoulder has three, the elbow has one and the wrist has three. Only two degrees of freedom were considered in the previous work. Moreover, the arm was supported horizontally. So, free movement in 3D space is still a necessity. And for 3D movements or posture control, compensation for gravity has to be considered. In this papre, four joint angles, one at the elbow and three at the shoulder were estimated from surface EMG signals of 12 flexor and extensor muscles during posture control in 3D space.

Many previous works state that a multiple Sidelobe canceller (MSLC) with two auxiliary antennas is successful in suppressing two interference signals received simultaneously by sidelobes of a main antenna. In this paper, we show that the MSLC does not always guarantee such capability in three dimensional applications where the incident direction of interference signals is defined by two angles (elevation and azimuth). We show the singularity of the autocorrelation matrix for the auxiliary channel signals induces the degradation of the capability by analyzing characteristics of MSLC's in three dimensional applications from the view point of the eigenvalue problem. To overcome this singularity, we propose a novel MSLC controlling the placement of auxiliary antennas by means of switching over three antennas arranged triangularly. Some simulations are conducted to show the effectiveness of the proposed MSLC.

Recent progress on the ultrahigh-speed optical transmission experiments are reviewed including the ultrashort pulse generation, high-speed timing extraction, all-optical multi/demultiplexing. Also discussed are the latest 100 Gbit/s experiments and a scope to higher bit-rate, longer distance optical transmission.

A new multiple-valued mask-ROM cell and a technique suitable for data detection are proposed. The information is programmed in each of the memory cells as both the threshold voltage and the channel length of the memory cell transistor, and the stored data are detected by selecting the bias condition of both the word-line and the data-line. The datum stored in the channel length is read-out using punch-through effect at the high drain voltage. The feasibility of this mask-ROM's is studied with device simulation and circuit simulation. With this design, it would be possible to get the high-density mask-ROM's, which might be faster in access speed and easier in fabrication process than the conventional ones. Therefore, this design is expected to be one of the most practical multiple-valued mask-ROM's.

We consider a class of unknown scenes Sk(n) with rectangular obstacles aligned with the axes such that Euclidean distance between the start point and the target is n, and any side length of each obstacle is at most k. We propose a strategy called the adaptive-bias heuristic for navigating a robot in such a scene, and analyze its efficiency. We show that a ratio of the total distance walked by a robot using the strategy to the shortest path distance between the start point and the target is at most 1+(3/5) k, if k=o(n) and if the start point and the target are at the same horizontal level. This ratio is better than a ratio obtained by any strategy previously known in the class of scenes, Sk(n), such that k=o(n).

This report describes 4-2 compressors composed of Complementary Pass-Transistor Logic (CPL). We will show that circuit designs of the 4-2 compressors can be optimized for high speed and small size using only exclusive-OR's and multiplexers. According to a circuit simulation with 0.8µm CMOS device parameters, the maximum propagation delay and the average power consumption per unit adder are 1.32 ns and 11.6 pJ, respectively.

In this paper, it is proven that the following three decision problems on validation of protocols with bounded capacity channels are NP-complete. (1) Given a protocol with the channel capacity being 1, determine whether or not there exist deadlocks in the protocol. (2) Given a protocol with the channel capacity being 1, determine whether or not there exist unspecified receptions in the protocol. (3) Given a protocol with the channel capacity being 2, determine whether or not there exist overflows such that the channel capacity is not bounded by 1 in the protocol. These results suggest that, even when all channeles in a protocol are bounded by 1 or 2, protocol validation should be in general interactable. It also clarifies the boundary of computational complexity of protocol validation problems because the channel capacity 0 does not allow protocols to transmit and recieve messages.

This paper investigates the accepting powers of one-way alternating multi-stack-counter automata (lamsca's) and one-way alternating multi-counter automata (lamsca's) which operate in realtime. For each k1, let 1ASCA (k, real) (1ACA(k, real)) denote the class of sets accepted by realtime one-way alternating k-stach-counter (k-counter) automata, and let 1USCA(k, real)(1UCA(k, real)) denote the class of sets accepted by realtime one-way alternating k-stack-counter (k-counter) automata with only universal states. We first investigate a relationship between the accepting powers of realtime lamsca's (lamca's) with only universal states, with only existential states, and with full alternation. We then investigate hierarchical properties based on the numbers of counters and stackcounters, and show, for example, that for each k1, 1USCA(k+1, real)-1ASCA(k, real)φ and 1UCA(k+1, real)-1ACA(k, real)φ. We finally investigate a relationship between the accepting powers of realtime lamsca's and lamca's, and show, for example, that there are no i and j such that 1UCA(i, real)=1USCA(j, real), and 1USCA(k, real)-1ACA(k, real)φ for each k1.

The planar point location problem is one of the most fundamental problems in computational geometry and stated as follows： Given a straight line planar graph (subdivision) with n vertices and an arbitary query point Q, determine the region containing Q. Many algorithms have been proposed, and some of them are known to be theoretically optimal (O(log n) search time, O(n) space and O(n log n) preprocessing time). In this paper, we implement several representative algorithms in C, and investigate their practical efficiencies by computational experiments on Voronoi diagrams with 210 - 217 vertices.

This paper presents an efficient algorithm for constructing at-most-k levels of an arrangement of n lines in the plane in time O(nk+n log n), which is optimal since Ω(nk) line segments are included there. The algorithm can sweep the at-most-k levels of the arrangement using O(n) space. Although Everett et al. recently gave an algorithm for constructing the at-most-k levels with the same time complexity independently, our algorithm is superior with respect to the space complexity as a sweep algorithm. Then, we apply the algorithm to a bipartitioning problem of a bichromatic point set： For r red points and b blue points in the plane and a directed line L, the figure of demerit fd(L) associated with L is defined to be the sum of the number of blue points below L and that of red ones above L. The problem we are going to consider is to find an optimal partitioning line to minimize the figure of demerit. Given a number k, our algorithm first determines whether there is a line whose figure of demerit is at most k, and further finds an optimal bipartitioning line if there is one. It runs in O(kn+n log n) time (n=r+b), which is subquadratic if k is sublinear.

In this letter, we present a distinct alternative of cross talk formulation of associative memory based on the outer product algorithm extended to the higher order and a performance evaluation in terms of the probability of exact data recall by using this formulation. The significant feature of these formulations is that both cross talk and the probability formulated are explicitly represented as the functional forms of Hamming distance between the memorized keys and the applied input key, and the degree of higher order correlation. Simulation results show that exact data retrieval ability of the associative memory using randomly generated data and keys is in well agreement with our theoretical estimation.

The origin of and a method of enhancing the Optical Beam Induced Resistance Change (OBIRCH) signal for defect observation in VLSI metal interconnections is discussed based on a numerical analysis of three-dimensional thermal conduction and experimental results. The numerical analysis shows that the OBIRCH signal originates from a slight increase in the resistance of the metal line caused by laser beam heating and that its effect is influenced by the temperature of the metal layer. Both simulations and experimental results suggest that cooling the sample is preferable to detect the OBIRCH signal. The decrease in the total resistance of the metal line without any change in the amount of the resistance increase under laser illumination is found to be the main cause of the OBIRCH signal enhancement under low temperature measurement.

A procedure for preparing a cross-sectional transmission electron microscopy (TEM) micrograph of a specific area is outlined. A specific area in a specimen has been very difficult to observe with TEM, because a particular small area cannot be preselected in the conventional specimen preparation technique using mechanical polishing, dimpling and ion milling. The technique in this paper uses a focused ion beam (FIB) to fabricate a cross-sectional specimen at a desired area. The applications of this specimen preparation technique are illustrated for investigations of particles in the process of fabricating devices and degraded aluminum/aluminum vias. The specimen preparation technique using FIB is useful for observing a specific area. This technique is also useful for shortening the time of specimen preparation and observing wide areas of LSI devices.

This paper presents an algorithm which sums up n binary values on an n m reconfigurable mesh in O(log n/(m log m)1/2) time. This algorithm also yields a corollary which states that n binary values can be summed up on an nlog2n/log log n reconfigurable mesh in constant time.