Material representations and algorithms are presented for simulation of nanometer lithography. Organic polymer resists are modeled as collections of overlapping spheres, with each sphere representing a polymer chain. Exposure and post-exposure bake steps are modeled at the nanometer scale for both positive and negative resists. The development algorithm is based on the Poisson removal probability for each sphere in contact with developer. The Poisson removal rate for a given sphere is derived from a mass balance relationship with a macroscopic development rate model. Simulations of electron beam lithography with (poly) methyl methacrylate and Shipley SAL-601 reveal edge roughness standard deviations from 2 to 3 nm, leading to linewidth peak-to-peak 3σ variation of 15 to 22 nm. Typical simulations require about 2 MBytes and under 5 minutes on a Sun Sparc 10/41 engineering workstation.

Tunneling generation becomes increasingly important in modern devices both as a source of leakage and for special applications. Mostly, the observed phenomena are attributed to band-to-band tunneling, although from early investigations of Esaki diodes it is well known that at lower field strengths trap-assisted tunneling is responsible for non-ideal IV-characteristics. In this paper we apply microscopic models of trap-assisted and band-to-band tunneling, which were derived from first-principle quantum-mechanical calculations, in a general multi-device simulator. Special simplified versions of the models were developed for the purpose of fast numerical computations. We investigate pn-junctions with different doping profiles to reveal the relative contribution of the two tunneling mechanisms. Simulated currents as function of voltage and temperature are presented for each individual process varying the basic physical parameters. It turns out that the slope of reverse IV-characteristics dominated by trap-assisted tunneling is similar to those which are determined by band-to-band tunneling, if the localized state of the recombination center is only weakly coupled to the lattice. In the model such a slope is produced by field-enhancement factors of the Shockley-Read-Hall lifetimes expressing the probability of tunneling into (or out of) excited states of the electron-phonon system. The temperature dependence of these field-enhancement factors compensates to a certain extent the expected strong temperature effect of the Shockley-Read-Hall process. The latter remains larger than the temperature variation of phonon-assisted band-to-band tunneling, but not as much as often stated. Consequently, the slope of the IV-characteristics and their temperature dependence are not the strong criteria to distinguish between trap-assisted and band-to-band tunneling. The origin of tunnel currents in silicon rather depends on the sum of physical conditions: junction gradient, nature and concentration of defects, temperature and voltage range.

Photonic ATM switching systems with Terabit/s throughput are desirable for future broadband ISDN systems. Since electronic LSI-based ATM switching systems are planned to have the throughput of 160Gb/s, a photonic ATM switching system should take the role of the highest layer in a hybrid switching network which includes electronic LSI-based ATM switching systems as its sub-system. This report discusses the state-of-the-art photonic devices needed for a frequency-self-routing ATM photonic switching system with maximum throughput of 5Tb/s. This kind of systems seems to be a moderate system for the first phase photonic switching system with no insuperable obstacle for initiating development, even though none of the devices and technologies required have yet been developed to meet the specifications. On the contrary, for realizing further enlarged throughput as the second-phase photonic switching system, there are huge fundamental research projects still remaining for establishing the technology utilizing the spectrum broadened over 120nm and highly-dense FDM technologies based on homodyne coherent detection, if supposing a simple architecture. "Ultra devices" seem to be the photonic devices based on new tailored materials of which gain and refractive index are designed to realize ultra-wide spectrum utilization.

A new kind of optical local area network (LAN), using a demand assign wavelength division multiple access (DA-WDMA) scheme, has been proposed. The proposed LAN consists of two parts; an ordinary standardized LAN and an overlaid network using wavelength division (WD) channels. The proposed network can provide bit-rate independent communication channels on the ordinary LAN without limiting the capacities for the other channels. It also exhibits upgrade possibilities from present standardized networks. An access controller, which consists of software in addition to the ordinary LAN controller, a digital signal processor (DSP) etc., was developed for DA-WDMA control. The network node operation has been demonstrated using guided-wave acousto-optic (AO) mode converters as a tunable wavelength add-drop multiplexer (ADM).

For IF direct sampling phase detection method (IFSM) which realizes the arithmetical operations with digital filters by direct A/D (Analog to Digital) conversion of IF (Intermediate Frequency) signal, the method to eliminate DC offset is proposed and developed by using the gate array. A principle of the proposed method and the results of the measurement are shown.

To realize a high performance optical subscriber network a route reconnect switch is desired which has bistability, polarization and wavelength independence and compactness. This paper proposes an electrocapillarity optical (ECO) switch, in which a micro-mirror formed by a mercury droplet is driven by electrocapillarity. This switch has a potential for use in bistable waveguide matrix switches, which are suitable for route reconnection in the optical subscriber network. A theoretical model is presented that the driving force of the electrocapillarity originates in an electrically induced gradient in the surface tension of the mercury-electrolyte interface where an electrical double layer is formed. The experimentally obtained relation between the flow velocity of a mercury droplet and the electric current in an electrocapillary system is well described by this model. A prototype of the ECO switch is made using a resin molded single-mode fiber with a slit sawed in it in which a electrocapillary system is made. Optical switching is demonstrated and possible improvements in switching performance are discussed.

An eye-contact technique using a blazed half-transparent mirror (BHM) is developed. This half-transparent mirror (HM) consists of an in-line array of many slanting micro-HMs. We fabricated a prototype system and confirmed the principle of this technique. The resolution of an image reflected by a BHM was simulated to determine how to improve the image quality and the factors degrading the resolution were clarified.

OTA (Operational Transconductance Amplifier) is a useful circuit in analog signal processing systems, especially in high-frequency applications. Important features of OTA are: infinite input impedance, electrically changeable transconductance (Gm), and much wider operation range without negative feedback such as in OPamp applications. The good linearity of OTA over wide input range is necessary to extend the application fields of OTA. Several techniques are developed to extend the input range with good linearity. In this paper, a highly-linear CMOS-OTA operating under 1 V power supply, is proposed. The concept of the proposed OTA is based on class-AB operation of two n-channel MOSFETs in the saturation region. By improving the input stage circuits, wide input range can be achieved. SPICE simulations are performed to verify the performance of the proposed OTA.

Two types of novel nVT level shift circuits based on the square law characteristics of MOSFETs have been proposed. These circuits generate VIN+nVT or VIN-nVT (where VT is a threshold voltage), if the input voltage is applied as the VIN. These circuits can be widely used in MOSFET characterization, compensating VT effect, VT measurement, level shifting, etc. Type 1 is directly derived from the nVT-sift circuit proposed by Wang. Type 2 can reduce a total chip area than type 1 and has a wider input range. SPICE simulations show that the proposed circuits have a very wide input range and a small power consumption.

This paper describes a segment driver IC for high-quality liquid-crystal-displays (LCDs). Major design issues in the segment driver IC are a wide signal bandwidth and excessive output-offset variation both within a chip and between chips. After clarifying the trade-off relation between the signal bandwidth and the output-offset variation originated from conventional sample-and-hold (S/H) circuits, two wide-band S/H circuits with low output-offset variation have been introduced. The basic ideas for the proposed S/H circuits are to improve timing of the sampling pulses applied to MOS analog switches and to prevent channel charge injection onto a storage capacitor when the switches turn off. The inter-chip offset-cancellation technique has been also introduced by using an additional S/H circuit. Two test chips were implemented using the above S/H circuits for demonstration purposes. The intra-chip output-offset standard deviation of 9.5 mVrms with a 3dB bandwidth of 50 MHz was achieved. The inter-chip output-offset standard deviation was reduced to 5.1 mVrms by using the inter-chip offset-cancellation technique. The evaluation of picture quality of an LCD using the chips shows the applicability of the proposed approaches to displays used for multimedia applications.

This paper describes a DBF (Digital Beamforming) technique as a spatial filtering in the radar systems. DBF for a beamformer and an adaptive processor are discussed. An architecture for the beamformer is proposed. The beamformer discussed consists of systolic arrays that can form beams arbitrarily. Antenna radiation patterns measured in an open site are shown. For the adaptive processor, Gram-Schmidt transformation method is attained by using systolic arrays. Proposed is a means to prevent target signals from being suppressed in cells of the systolic arrays and to achieve the convergent characteristics independent of the magnitude of undesired signal power. In order to demonstrate the performance of the proposed processor, a test model of the adaptive processor was developed and tested in multiple undesired signal environment. Test results are indicated.

The Synchronous Optical Network (SONET) technology offers technical possibilities to build high speed transport networks and enables the operator to react quickly to the customers' capacity requirements. Furthermore the advanced SONET equipment, with standardized control and operation features, provides opportunities for new services, such as broadband services, and cost-effective ways to enhance existing services, such as network survivability improvement. But SONET technology can also create a certain degree of complexity in building cost-efficient network, especially in case of SONET Self-Healing Ring (SHR). It is a challenge for network planner to find an effective way to select the most economical SONET ring, or combination of rings, for given demands between a set of nodes that are supposed to be connected in a certain type of ring configuration. Three types of ring are standard today: path unidirectional, 2-fiber line protection bidirectional and 4-fiber line protection bidirectional. For a given network, the choosing of ring architecture based on economical considerations involves two major factors. They are capacity requirement and equipment cost. Capacity requirements of different SONET ring architectures depend upon different conditions. While facility line rate, which is a key factor in deciding what kind self-healing ring can be deployed economically on these requirements. Routing decisions play a key role in deciding the ring capacities required, especially for bidirectional rings. In the paper, we will make the economic study on how SONET SHR architecture works out with a variety of demand patterns, to find criteria for ring selection. We first present two efficient demand loading algorithms for BSHR capacity calculation, and then analyze the results from their application on a variety of demand patterns. The economic study for SONET SHR networks based on different architectures are also discussed.

An HDTV still-picture camera that uses four PAL CCD sensors has been developed for use as a high-speed, high-resolution image reader. The CCD sensors are optically coupled to a single lens by a pyramidal mirror. Each CCD sensor reads a quarter of the image and the four quarter-images are combined into one HDTV picture. Discontinuities at the lines where the four images join can be eliminated by white- and dark-level correction and gamma correction. Moreover, smoothing processing using a weighted-mean method is performed to produce a seamless picture. With this processing the camera can consistently produce seamless pictures.

A software package has been developed for simulating complex silicon and heterostructure devices in 3D. Device geometries are input with a mouse-driven geometric modeler, thus simplifying the definition of complex 3D shapes. Single components of the device are assembled through boolean operations. Tetrahedra are used for grid generation, since any plane-faced geometry can be tessellated with tetrahedra, and point densities can be adapted locally. The use of a novel octree-like data structure leads to oriented grids where desirable. Bad angles that prevent the convergence of the control volume integration scheme are eliminated mostly through topological transformations, thus avoiding the insertion of many redundant grid points. The discretized drift-diffusion equations are solved with an iterative method, using either a decoupled (or Gummel) scheme, or a fully coupled Newton scheme. Alternatively, generated grids can be submitted to a Laplace solver in order to calculate wire capacitances and resistances. Several examples of results illustrate the flexibility and effectiveness of this approach.

This paper introduces a constraint logic programming (CLP) language cu-Prolog as an implementation framework for constraint-based natural language processing. Compared to other CLP languages, cu-Prolog has several unique features. Most CLP languages take algebraic equations or inequations as constraints. cu-Prolog, on the other hand, takes Prolog atomic formulas in terms of user-defined predicates. cu-Prolog, thus, can describe symbolic and combinatorial constraints occurring in the constraint-based grammar formalisms. As a constraint solver, cu-Prolog uses the unfold/fold transformation, which is well known as a program transformation technique, dynamically with some heuristics. To treat the information partiality described with feature structures, cu-Prolog uses PST (Partially Specified Term) as its data structure. Sections 1 and 2 give an introduction to the constraint-based grammar formalisms on which this paper is based and the outline of cu-Prolog is explained in Sect. 3 with implementation issues described in Sect. 4. Section 5 illustrates its linguistic application to disjunctive feature structure (DFS) and parsing constraint-based grammar formalisms such as Japanese Phrase Structure Grammar (JPSG). In either application, a disambiguation process is realized by transforming constraints, which gives a picture of constraint-based NLP.

This paper describes a new free-space optical switch structure based on cascaded beam shifters (each consists of a liquid-crystal polarization controller array and a birefringent plate). This structure comprises 2-input, 2-output switching elements that are locally connected by links. It is applicable to a variety of switching networks, such as a Clos network. The switching network based on this structure is an analog switch that is transparent to signal format, bit rate, and modulation type, so it can handle various types of optical signals. Theoretical feasibility studies indicate that compact large-scale switches (i.e., 100-1000 ports) with relay lens systems can be implemented using beam shifters with a 0.4-dB insertion loss and a 30-dB extinction ratio. Experimental feasibility studies indicate that a 1024-cell beam shifter module with a 0.5-dB insertion loss and a 23-dB extinction ratio is possible at present. An alignment-free assembly technique using precise alignment guides is also confirmed. An experimental 8-stage, 1024-input 256-output concentrator shows low insertion loss characteristics (6.8dB on average) owing to the low-loss beam shifters and the alignment-free assembly technique. Practical switching networks mainly require the improvement of the extinction ratio of the beam shifter module and the development of a fiber pig-tailing technique. This switch structure is applicable to transparent switching networks such as subscriber line concentrators and inter-module connectors.

The modular and growable photonic ATM switch architecture described in this paper uses both time-division and wavelength-division multiplexing technologies, so the switch capacity can be expanded in both the time and frequency domains. It uses a new implementation of output buffering scheme that overcomes the bottleneck in receiving and storing concurrent ultra fast optical cells. The capacity in one stage of a switch with this architecture can be increased from 32 gigabits per second to several terabits per second in a modular fashion. The proposed switch structure with output channel grouping can greatly reduce the amount of hardware and still guarantee the cell sequence.

The requirement of structural boundedness or passivity leads to important classes of digital filters among which are the wave digital (WD) filters and the LBR cascade structures having low coefficient sensitivity. Contrary to the WD filters, the LBR filters are directly synthesized in z-domain and several authors presented different approaches for a better understanding of the synthesis procedure especially for complex transfer functions. Some tentatives were also made to give parallels between passive analog and digital filters (i.e. WD or LBR filters). A general approach to LBR synthesis with transmission zeros not necessarily on the unit circle is presented along with some explicit expressions for the LBR (and the generalized complex counterpart LBC) filter parameters for the realization of an input transfer function. The results can be of interest in automated procedures for low sensitivity digital filter design.

A simulation study on cylindrical semiconductor devices is described, where the internal behavior of power devices are analyzed under steady-state condition with considering heat generation. In simulation, circular cylindrical coordinate is used to consider the effect of three-dimensional spreading current flow with keeping calculation time and memory as in two-dimensional simulation. Numerical model is based on the well-known set of Shockley-Roosbroeck semiconductor equations--continuity equations for carriers and Poisson's equation, along with heat flow equation. Drift-diffusion approximation of carrier transport equations is used, taking temperature field as a driving force for carriers into account. Using the cylindrical simulator, numerical analysis of power MOSFETs, which integrate zener diodes to improve the avalanche capability, has been carried out. Results showed that, a parasitic bipolar transistor turns on under forward-biased condition in a power MOSFET with a zener diode. The highest lattice temperature takes place at source edge. Under reverse-biased condition, breakdown occurs at doughnut area around the bottom of source contact (at the upper region of zener junction), and the avalanche current flows detouring the base region of parasitic bipolar transistor which implies that secondary breakdown will be suppressed. The highest lattice temperature region under reverse-biased conditions is the same as the breakdown region. Without zener diodes, on the other hand, breakdown occurs ringing about the edge of source region, and the avalanche current flows through the base region of parasitic bipolar transistor which implies that even MOSFETs may suffer from the secondary breakdown. As channel length becomes short, breakdown caused by punchthrough becomes dominant at the edge of source region.

A two-dimensional self-aligned silicide (SALICIDE) model has been developed using the general-purpose process simulator OPUS. A new two-dimensional growth model is proposed. Utilizing a newly-difined effective silicide thickness, the model accounts both silicon-diffusion and metal-diffusion limited silicide growth. Silicide lateral-growth along a sidewall spacer is successfully simulated for Si-diffusion limited silicide growth. Complete MOSFET process simulation with a SALICIDE process is demonstrated for the first time.