In this letter, the problem of feature quantization in robust hashing is studied from the perspective of approximate nearest neighbor (ANN). We model the features of perceptually identical media as ANNs in the feature set and show that ANN indexing can well meet the robustness and discrimination requirements of feature quantization. A feature quantization algorithm is then developed by exploiting the random-projection based ANN indexing. For performance study, the distortion tolerance and randomness of the quantizer are analytically derived. Experimental results demonstrate that the proposed work is superior to state-of-the-art quantizers, and its random nature can provide robust hashing with security against hash forgery.

Accurate modeling of sea clutter and detection of low observable targets within sea clutter are the major goals of radar signal processing applications. Recently, fractal geometry has been applied to the analysis of high range resolution radar sea clutters. The box-counting method is widely used to estimate fractal dimension but it has some drawbacks. We explain the drawbacks and propose a new fractal dimension based detector to increase detection performance in comparison with traditional detectors. Both statistically generated and real data samples are used to compare detector performance.

We propose a chip identification (ID) generating scheme with random variation of transistor characteristics in SRAM bitcells. In the proposed scheme, a unique fingerprint is generated by grounding both bitlines in write operations. Through minor modifications, this scheme can be implemented for existing SRAMs. It has high speed, and it can be implemented in a very small area overhead. The generated fingerprint mainly reflects threshold voltages of load transistors in the bitcells. We fabricated test chips in a 65-nm process and obtained 12,288 sets of unique 128-bit fingerprints, which are evaluated in this paper. The failure rate of the IDs is found to be 2.110-12.

This paper proposes applying intra-subframe frequency hopping (FH) to closed-loop (CL) type transmit diversity using codebook based precoding for a shared channel carrying user traffic data in discrete Fourier transform (DFT)-precoded Orthogonal Frequency Division Multiple Access (OFDMA). In the paper, we present two types of precoding schemes associated with intra-subframe FH: individual precoding vector selection between 2 slots where a 1-ms subframe comprises 2 slots among the reduced precoding codebooks, and common precoding vector selection between 2 slots. We investigate the effect of intra-subframe FH on the codebook based transmit diversity in terms of the average block error rate (BLER) performance while maintaining the same number of feedback bits required for notification of the selected precoding vector as that for the conventional CL transmit diversity without FH. Computer simulation results show that the codebook based transmit diversity with intra-subframe FH is very effective in decreasing the required average received signal-to-noise power ratio (SNR) when the fading maximum Doppler frequency, fD, is higher than approximately 50 Hz both for 2- and 4-antenna transmission in the DFT-precoded OFDMA.

The interference rejection combining (IRC) receiver, which can suppress inter-cell interference, is effective in improving the cell-edge user throughput. The IRC receiver is typically based on the minimum mean square error (MMSE) criteria, and requires a covariance matrix including the interference signals, in addition to a channel matrix from the serving cell. Therefore, in order to clarify the gain from the IRC receiver, the actual estimation error of these matrices should be taken into account. In a system performance evaluation, the link performance modeling of the IRC receiver, i.e., the output signal-to-interference-plus-noise power ratio (SINR) after IRC reception including the estimation errors, is very important in evaluating the actual performance of the IRC receiver in system level simulations. This is because these errors affect the suppression of the interference signals for the IRC receiver. Therefore, this paper investigates and proposes IRC receiver modeling schemes for the covariance matrix and channel estimation errors. As the modeling scheme for the covariance matrix, we propose a scheme that averages the conventional approximation using the complex Wishart distribution in the frequency domain to address issues that arise in a frequency selective fading channel. Furthermore, we propose a modeling scheme for the channel estimation error according to the ideal channel response of all cells and a channel estimation filter to address channel fading fluctuations. The results of simulations assuming the LTE/LTE-Advanced downlink with two transmitter and receiver antenna branches show that the proposed modeling scheme for the covariance matrix estimation error accurately approximates the performance of a realistic IRC receiver, which estimates the covariance matrix and channel matrix of the serving cell based on the demodulation reference signal (DM-RS), even in a frequency selective fading channel. The results also show that the proposed modeling scheme for the channel estimation error is a robust scheme in terms of the r.m.s. delay spread of a channel model compared to the scheme using the mean square error (MSE) statistic of the estimated channel coefficients based on a channel estimation filter.

SRAM-based field programmable gate arrays (FPGAs) are vulnerable to a soft-error induced by radiation. Techniques for designing dependable circuits, such as triple modular redundancy (TMR) with scrubbing, have been studied extensively. However, currently available evaluation techniques that can be used to check the dependability of these circuits are inadequate. Further, their results are restrictive because they do not represent the result in terms of general reliability indicator to decide whether the circuit is dependable. In this paper, we propose an evaluation method that provides results in terms of the realistic failure in time (FIT) by using reconfiguration-based fault-injection analysis. Current fault-injection analyses do not consider fault accumulation, and hence, they are not suitable for evaluating the dependability of a circuit such as a TMR circuit. Therefore, we configure an evaluation system that can handle fault-accumulation by using frame-based partial reconfiguration and the bootstrap method. By using the proposed method, we successfully evaluated a TMR circuit and could discuss the result in terms of realistic FIT data. Our method can evaluate the dependability of an actual system, and help with the tuning and selection in dependable system design.

In this paper, an all-digital wireless transceiver for near-field communication (NFC) is presented. A novel modulation technique that allows employing only all-digital components in the transceiver is used. The front-end uses all-digital sub-sampling for carrier demodulation, which does not need synchronization circuitry. Burst-errors generated by the front-end are corrected in baseband using hamming code and interleaving techniques. Experimentally, the all-digital transceiver was tested on FPGAs that performed successful wireless communication at range/diameter equal to 1, which is higher than recent NFC research. Our transceiver uses only all-digital components, and consumes less area compared to other research.

Solving image recovery problems requires the use of some efficient regularizations based on a priori information with respect to the unknown original image. Naturally, we can assume that an image is modeled as the sum of smooth, edge, and texture components. To obtain a high quality recovered image, appropriate regularizations for each individual component are required. In this paper, we propose a novel image recovery technique which performs decomposition and recovery simultaneously. We formulate image recovery as a nonsmooth convex optimization problem and design an iterative scheme based on the alternating direction method of multipliers (ADMM) for approximating its global minimizer efficiently. Experimental results reveal that the proposed image recovery technique outperforms a state-of-the-art method.

A specific physical layer network coding (PNC) scheme is proposed for the two-way relay channel. Unlike the traditional binary PNC that focuses mainly on BPSK modulation, the proposed PNC scheme is tailored for general MPSK modulation. In particular, the product of the two modulated signals is considered as a network-coded symbol. The proposed network coding operation occurs naturally in the inner or outer product of the received signal. A novel PNC-specific detection principle is then developed to estimate the network-coded symbol. Simulations show that the proposed scheme achieves almost optimal performance in terms of end-to-end bit error rate (BER), where the relay node is equipped with multiple antennas.

A diversity scheme with Fractional Sampling (FS) in OFDM receivers has been investigated recently. FS path diversity makes use of the imaging components of the desired signal transmitted on the adjacent channel. To increase the diversity gain with FS the bandwidth of the transmit signal has to be enlarged. This leads to the reduction of spectrum efficiency. In this paper non-orthogonal access over multiple channels in the frequency domain with iterative interference cancellation (IIC) and FS is proposed. The proposed scheme transmits the imaging component non-orthogonally on the adjacent channel. In order to accommodate the imaging component, it is underlaid on the other desired signal. Through diversity with FS and IIC, non-orthogonal access on multiple channels is realized. Our proposed scheme can obtain diversity gains for non-orthogonal signals modulated with QPSK.

In this paper, we have addressed the problem of ordering transactions in network-on-chips (NoCs) for post-silicon validation. The main idea is to extract the order of the transactions from the local partial orders in each NoC tile based on a set of “happened-before” rules, assuming transactions do not have a timestamp. The assumption is based on the fact that implementation and usage of a global time as timestamp in such systems may not be practical or efficient. When a new transaction is received in a tile, we send special messages to the neighboring tiles to inform them regarding the new transaction. The process of sending those special messages continues recursively in all the tiles that receive them until another such special message is detected. This way, we relate local orders of different tiles with each other. We show that our method can reconstruct the correct transaction orders when communication delays are deterministic. We have shown the effectiveness of our method by correctly ordering the transaction in NoCs with mesh and torus topologies with different sizes from 5*5 to 9*9. Also, we have implemented the proposed method in hardware to show its feasibility.

A high-speed low-complexity time-multiplexing Reed-Solomon-based forward error correction architecture based on the pipelined truncated inversionless Berlekamp-Massey algorithm is presented in this paper. The proposed architecture has very high speed and very low hardware complexity compared with conventional Reed-Solomon-based forward error correction architectures. Hardware complexity is improved by employing a truncated inverse Berlekamp-Massey algorithm. A high-speed and high-throughput data rate is facilitated by employing a three-parallel processing pipelining technique and modified syndrome computation block. The time-multiplexing method for pipelined truncated inversionless Berlekamp-Massey architecture is used in the parallel Reed-Solomon decoder to reduce hardware complexity. The proposed architecture has been designed and implemented with 90-nm CMOS technology. Synthesis results show that the proposed 16-channel Reed-Solomon-based forward error correction architecture requires 417,600 gates and can operate at 640 MHz to achieve a throughput of 240 Gb/s. The proposed architecture can be readily applied to Reed-Solomon-based forward error correction devices for next-generation short-reach optical communications.

In OFDM systems, the correlation of cyclic prefix (CP) with its corresponding part at the end of the symbol can be used to estimate the maximum Doppler spread. However, the estimation accuracy of this CP based method is seriously affected by the inter-symbol interference (ISI) generated in the multipath channel. In this letter, we propose an enhanced CP based method which is immune to the ISI and can hence obtain an unbiased estimate of the auto-correlation function in multipath channels.

In recent years, the demand for low-power design has remained undiminished. In this paper, a pseudo power gating (SPG) structure using a normal logic cell is proposed to extend the power gating to an ultrafine grained region at the gate level. In the proposed method, the controlling value of a logic element is used to control the switching activity of modules computing other inputs of the element. For each element, there exists a submodule controlled by an input to the element. Power reduction is maximized by controlling the order of the submodule selection. A basic algorithm and a switching activity first algorithm have been developed to optimize the power. In this application, a steady maximum depth constraint is added to prevent the depth increase caused by the insertion of the control signal. In this work, various factors affecting the power consumption of library level circuits with the SPG are determined. In such factors, the occurrence of glitches increases the power consumption and a method to reduce the occurrence of glitches is proposed by considering the parity of inverters. The proposed SPG method was evaluated through the simulation of the netlist extracted from the layout using the VDEC Rohm 0.18 µm process. Experiments on ISCAS'85 benchmarks show that the reduction in total power consumption achieved is 13% on average with a 2.5% circuit delay degradation. Finally, the effectiveness of the proposed method under different primary input statistics is considered.

A low-cost and low-power via-programmable structured ASIC architecture named “VPEX3” and a VPEX3-specific CAD system are developed. In the VPEX3 architecture, which is an improved version of the old VPEX and VPEX2 architectures, an arbitrary logic function including sequential logic can be programmed by three via layers. The logic elements (LEs) of VPEX3 are 60% smaller than those of the previous VPEX2, which can be programmed by two via layers. In this paper, we describe a global architecture named Logic Array Block (LAB) composed of LE matrices. The clock lines are buffered in the buffering region on the left and right sides of LAB. Next, a VPEX3-specific CAD system utilizing an academic placement tool named “CAPO” and the “FGR” global router is developed. Since these tools are originally designed for ASICs, we developed CAD tools for supporting a structured ASIC architecture. In particular, we developed a detailed router that assigns via positions on the via-programmable routing fabric. Our CAD system successfully converts the HDL design to GDS-II data format including via-1, 2, 3 layouts, and the successful verification of LVS and DRC on GDSII is achieved. The performance of the VPEX3 architecture and the CAD system is evaluated using ISCAS benchmark circuits. The developed CAD system is used to successfully design a test chip composed of 130110 LEs.

In this paper, we present a transmission scheme for a multiple-input multiple-output (MIMO) quasi-static fading channel with imperfect channel state information at the transmitter (CSIT). In this scheme, we develop a precoder structure to exploit the available CSIT and apply spatial coupling for further performance enhancement. We derive an analytical evaluation method based on extrinsic information transfer (EXIT) functions, which provides convenience for our precoder design. Furthermore, we observe an area property indicating that, for a spatially coupled system, the iterative receiver can perform error-free decoding even the original uncoupled system has multiple fixed points in its EXIT chart. This observation implies that spatial coupling is useful to alleviate the uncertainty in CSIT which causes difficulty in designing LDPC code based on the EXIT curve matching technique. Numerical results are presented, showing an excellent performance of the proposed scheme in MIMO fading channels with imperfect CSIT.

This paper proposes a method for reconstructing accurate 3D surface points. To this end, robust and dense reconstruction with Shape-from-Silhouettes (SfS) and accurate multiview stereo are integrated. Unlike gradual shape shrinking and/or bruteforce large space search by existing space carving approaches, our method obtains 3D points by SfS and stereo independently, and then selects correct ones from them. The point selection is achieved in accordance with spatial consistency and smoothness of 3D point coordinates and normals. The globally optimized points are selected by graph-cuts. Experimental results with several subjects containing complex shapes demonstrate that our method outperforms existing approaches and our previous method.

This paper presents a blocked united algorithm for the all-pairs shortest paths (APSP) problem. This algorithm simultaneously computes both the shortest-path distance matrix and the shortest-path construction matrix for a graph. It is designed for a high-speed APSP solution on hybrid CPU-GPU systems. In our implementation, two most compute intensive parts of the algorithm are performed on the GPU. The first part is to solve the APSP sub-problem for a block of sub-matrices, and the other part is a matrix-matrix “multiplication” for the APSP problem. Moreover, the amount of data communication between CPU (host) memory and GPU memory is reduced by reusing blocks once sent to the GPU. When a problem size (the number of vertices in a graph) is large enough compared to a block size, our implementation of the blocked algorithm requires CPU GPU exchanging of three blocks during a block computation on the GPU. We measured the performance of the algorithm implementation on two different CPU-GPU systems. A system containing an Intel Sandy Bridge CPU (Core i7 2600K) and an AMD Cayman GPU (Radeon HD 6970) achieves the performance up to 1.1 TFlop/s in a single precision.

In this paper, using the Linear Time Variant (LTV) phase noise model and considering higher order harmonics generated by the oscillator output signal, a more general formula for transformation of the excess phase to the output signal is presented. Despite the basic LTV model which assumes that the total carrier power is within the fundamental harmonic, in the proposed model, the total carrier power is assumed to be distributed among all output harmonics. For the first harmonic, the developed expressions reduce to the basic LTV formulas. Simulation and experimental results are used to ensure the validity of the model.

A fractional-N phase-locked loop (PLL) is designed for the DigRF interface. The digital part of the PLL mainly consists of a dual-mode phase frequency detector (PFD), a digital counter, and a digital delta-sigma modulator (DSM). The PFD can operate on either 52 MHz or 26 MHz reference frequencies, depending on its use of only the rising edge or both the rising and the falling edges of the reference clock. The interface between the counter and the DSM is designed to give enough timing margin in terms of the signal round-trip delay. The circuitry is implemented using a 90-nm CMOS process technology with a 1.2-V supply, draining 1 mA.