In advanced ASIC/SoC physical designs, interconnect parasitic extraction is one of the important factors to determine the accuracy of timing analysis. We present a formula-based method to efficiently extract interconnect capacitances of interconnects with dummy fills for VLSI designs. The whole flow is as follows: 1) in each process, obtain capacitances per unit length using a 3-D field solver and then create formulas, and 2) in the actual design phase, execute a well-known 2.5-D capacitance extraction. Our results indicated that accuracies of the proposed formulas were almost within 3% error. The proposed formula-based method can extract interconnect capacitances with high accuracy for VLSI circuits. Moreover, we present formulas to evaluate the effect of dummy fills on interconnect capacitances. These can be useful for determining design guidelines, such as metal density before the actual design, and for analyzing the effect of each structural parameter during the design phase.

We have proposed a neural network called the Lagrange programming neural network with polarized high-order connections (LPPH) for solving the satisfiability problem (SAT) of propositional calculus. The LPPH has gradient descent dynamics for variables and gradient ascent dynamics for Lagrange multipliers, which represent the weights of the clauses of the SAT. Each weight wr increases according to the degree of unsatisfaction of clause Cr. This causes changes in the energy landscape of the Lagrangian function, on which the values of the variables change in the gradient descent direction. It was proved that the LPPH is not trapped by any point that is not a solution of the SAT. Experimental results showed that the LPPH can find solutions faster than existing methods. In the LPPH dynamics, a function hr(x) calculates the degree of unsatisfaction of clause Cr via multiplication. However, this definition of hr(x) has a disadvantage when the number of literals in a clause is large. In the present paper, we propose a new definition of hr(x) in order to overcome this disadvantage using the "min" operator. In addition, we extend the LPPH to solve the constraint satisfaction problem (CSP). Our neural network can update all neurons simultaneously to solve the CSP. In contrast, conventional discrete methods for solving the CSP must update variables sequentially. This is advantageous for VLSI implementation.

Displaced subdivision surface representation [13] is a new form of representing a polygonal surface model, where a detailed surface model is defined as a scaler-valued displacement map over a smooth domain surface; it puts forth a number of attractive features for editing, geometry compression, animation, scalability, and adaptive rendering of polygonal models. The construction of the smooth domain surface is a challenging task in the conversion process of a detailed polygonal surface model into this representation. In this paper, we propose a new efficient method for defining the smooth domain surface based on -subdivision scheme. The proposed algorithm not only performs better in terms of the quality of the generated surfaces but is computationally more efficient and occupies less memory as compared to the original algorithm [13] and generates surfaces with more levels of detail due to the specific nature of -subdivision when the prescribed target complexity of the generated mesh must not be exceeded. To corroborate the efficiency and the quality of the new technique, the conversion results for several public domain models have been presented.

This paper describes a new talker direction estimation method for front-end processing to capture distant-talking speech by using a microphone array. The proposed method consists of two algorithms: One is a TDOA (Time Delay Of Arrival) estimation algorithm based on a weighted CSP (Cross-power Spectrum Phase) analysis with an average speech spectrum and CSP coefficient subtraction. The other is a talker direction estimation algorithm based on ML (Maximum Likelihood) estimation in a time sequence of the estimated TDOAs. To evaluate the effectiveness of the proposed method, talker direction estimation experiments were carried out in an actual office room. The results confirmed that the talker direction estimation performance of the proposed method is superior to that of the conventional methods in both diffused- and directional-noise environments.

A novel concurrent core test approach is proposed to reduce the test cost of SOC. Prior to test, the test sets corresponding to cores under test (CUT) are merged by using the proposed merging algorithm to obtain a minimum merged test set. During test, the proposed scan tree architecture is employed to support the concurrent core test using the merged test set. The approach achieves concurrent core test with one scan input and low hardware overhead. Moreover, the approach does not need any additional test generation, and it can be used in conjunction with general compression/decompression techniques to further reduce test cost. Experimental results for ISCAS 89 benchmarks have proven the efficiency of the proposed approach.

This paper discusses propagation delay error, transient response, and power consumption distribution due to inductive effects in optimal buffered on-chip interconnects. Inductive effect is said to be important to consider in deep submicron (DSM) VLSI design. However, study shows that the effect decreases and can be neglected in next technology nodes for such conditions.

We developed two types of practical maximum-likelihood detectors (MLD) for multiple-input multiple-output (MIMO) systems, using a field programmable gate array (FPGA) device. For implementations, we introduced two simplified metrics called a Manhattan metric and a correlation metric. Using the Manhattan metric, the detector needs no multiplication operations, at the cost of a slight performance degradation within 1 dB. Using the correlation metric, the MIMO-MLD can significantly reduce the complexity in both multiplications and additions without any performance degradation. This paper demonstrates the bit-error-rate performance of these MLD prototypes at a 1 Gbps-order real-time processing speed, through the use of an all-digital baseband 44 MIMO testbed integrated on the same FPGA chip.

This paper presents a simple method to determine weights of single carrier multiple input multiple output (MIMO) broadband communication systems adopting tapped delay line (TDL) structure in receiver side for the effective communication under frequency selective fading (FSF) environment. First, assuming the perfect knowledge of the channel matrix in both arrays, an iterative design method of transmitter and receiver weights is proposed. In this approach, both weights are determined alternately to maximize signal to noise plus interference ratio (SINR) by fixing the weight of one side while optimizing the other, and this operation is repeated until SINR converges. Next, considering the case of uninformed transmitter, maximum SINR design method of MIMO system is extended for space time block coding (STBC) scheme working under FSF. Through computer simulations, it is demonstrated that the proposed schemes achieves higher SINR than conventional method with delay-less structure, particularly for the fading with long duration.

With the application of optical add-drop multiplexers, wavelength assignment has become an important issue in SONET/WDM design. Among wavelength assignment methods, circle construction is of great importance. In this paper, we propose a novel matrix based circle construction algorithm for all-to-all uniform traffic in a bidirectional SONET/WDM ring.

This paper presents a new bearing fault detection algorithm based on analyzing singular points of vibration signals using the Haar wavelet. The proposed Haar Fault Detection (HFD) algorithm is compared with a previously-developed algorithm associated with the Morlet wavelet. We also substitute the Haar wavelet with Daubechies wavelets with larger compact supports and evaluate the results. Simulations carried on real data demonstrate that the HFD algorithm achieves a comparable accuracy while having a lower computational cost. This makes the HFD algorithm an appropriate candidate for fast processing of bearing faults.

This paper presents a high-accuracy 3D (three-dimen-sional) measurement system using multi-camera passive stereo vision to reconstruct 3D surfaces of free form objects. The proposed system is based on an efficient stereo correspondence technique, which consists of (i) coarse-to-fine correspondence search, and (ii) outlier detection and correction, both employing phase-based image matching. The proposed sub-pixel correspondence search technique contributes to dense reconstruction of arbitrary-shaped 3D surfaces with high accuracy. The outlier detection and correction technique contributes to high reliability of reconstructed 3D points. Through a set of experiments, we show that the proposed system measures 3D surfaces of objects with sub-mm accuracy. Also, we demonstrate high-quality dense 3D reconstruction of a human face as a typical example of free form objects. The result suggests a potential possibility of our approach to be used in many computer vision applications.

A new wideband signal DOA estimation algorithm based on modified quantum genetic algorithm (MQGA) is proposed in the presence of the errors and the mutual coupling between array elements. In the algorithm, the narrowband signal subspace fitting method is generalized to wideband signal DOA finding according to the character of space spectrum of wideband signal, and so the rule function is constructed. Then, the solutions is encoded onto chromosomes as a string of binary sequence, the variable quantum rotation angle is defined according to the distribution of optimization solutions. Finally, we use the MQGA algorithm to solve the nonlinear global azimuths optimization problem, and get optimization azimuths by fitness values. The computer simulation results illustrated that the new algorithm have good estimation performance.

There are many system proposals for satellite-based broadband communications that promise high capacity and ease of access. Many of these proposals require advanced switching technology and signal processing on-board the satellite(s). One solution is based on a geo-synchronous (GEO) satellite system equipped with on-board processing and on-board switching. An important feature of this system is allowing for a maximum number of simultaneous users, hence, requiring effective medium access control (MAC) layer protocols for connection admission control (CAC) and bandwidth on demand (BoD) algorithms. In this paper, an integrated CAC and BoD algorithm is proposed for a broadband satellite communication system with heterogeneous traffic. A detailed modeling and simulation approach is presented for performance evaluation of the integrated CAC and BoD algorithm based on heterogeneous traffic types. The proposed CAC and BoD scheme is shown to be able to efficiently utilize available bandwidth and to gain high throughput, and also to maintain good Grade of Service (GoS) for all the traffic types. The end-to-end delay for real-time traffic in the system falls well within ITU's Quality of Service (QoS) specification for GEO-based satellite systems.

The objective of this paper is to present a decision support system which uses a computer-based procedure to detect tumor blocks or lesions in digitized medical images. The authors developed a simple method with a low computation effort to detect tumors on T2-weighted Magnetic Resonance Imaging (MRI) brain images, focusing on the connection between the spatial pixel value and tumor properties from four different perspectives: 1) cases having minuscule differences between two images using a fixed block-based method, 2) tumor shape and size using the edge and binary images, 3) tumor properties based on texture values using spatial pixel intensity distribution controlled by a global discriminate value, and 4) the occurrence of content-specific tumor pixel for threshold images. Measurements of the following medical datasets were performed: 1) different time interval images, and 2) different brain disease images on single and multiple slice images. Experimental results have revealed that our proposed technique incurred an overall error smaller than those in other proposed methods. In particular, the proposed method allowed decrements of false alarm and missed alarm errors, which demonstrate the effectiveness of our proposed technique. In this paper, we also present a prototype system, known as PCB, to evaluate the performance of the proposed methods by actual experiments, comparing the detection accuracy and system performance.

Text detection in color images has become an active research area in the past few decades. In this paper, we present a novel approach to accurately detect text in color images possibly with a complex background. The proposed algorithm is based on the combination of connected component and texture feature analysis of unknown text region contours. First, we utilize an elaborate color image edge detection algorithm to extract all possible text edge pixels. Connected component analysis is performed on these edge pixels to detect the external contour and possible internal contours of potential text regions. The gradient and geometrical characteristics of each region contour are carefully examined to construct candidate text regions and classify part non-text regions. Then each candidate text region is verified with texture features derived from wavelet domain. Finally, the Expectation maximization algorithm is introduced to binarize each text region to prepare data for recognition. In contrast to previous approach, our algorithm combines both the efficiency of connected component based method and robustness of texture based analysis. Experimental results show that our proposed algorithm is robust in text detection with respect to different character size, orientation, color and language and can provide reliable text binarization result.

We propose a cell library development methodology for throughput enhancement of character projection equipment. First, an ILP (Integer Linear Programming)-based cell selection is proposed for the equipment for which both of the CP (Character Projection) and VSB (Variable Shaped Beam) methods are available, in order to minimize the number of electron beam (EB) shots, that is, time to fabricate chips. Secondly, the influence of cell directions on area and delay time of chips is examined. The examination helps to reduce the number of EB shots with a little deterioration of area and delay time because unnecessary directions of cells can be removed. Finally, a case study is shown in which the numbers of EB shots are shown for several cases.

This paper describes a newly developed automatic direction control scheme for bi-directional bus repeaters that uses dynamic collaborative driving techniques. Repeater directions are rapidly determined by detecting the direction of control signal propagation through an additional control signal line that is driven by dynamic collaborative drivers. Application to an on-chip peripheral bus reduces control circuit transistor counts by about 75% and the number of control signal lines by about 50% without loss of speed. Experimental results for a 0.18-µm CMOS implementation indicate that the proposed scheme is four times faster than a conventional scheme with no bi-directional bus repeaters.

Acoustic modeling in speech recognition uses very little knowledge of the speech production process. At many levels our models continue to model speech as a surface phenomenon. Typically, hidden Markov model (HMM) parameters operate primarily in the acoustic space or in a linear transformation thereof; state-to-state evolution is modeled only crudely, with no explicit relationship between states, such as would be afforded by the use of phonetic features commonly used by linguists to describe speech phenomena, or by the continuity and smoothness of the production parameters governing speech. This survey article attempts to provide an overview of proposals by several researchers for improving acoustic modeling in these regards. Such topics as the controversial Motor Theory of Speech Perception, work by Hogden explicitly using a continuity constraint in a pseudo-articulatory domain, the Kalman filter based Hidden Dynamic Model, and work by many groups showing the benefits of using articulatory features instead of phones as the underlying units of speech, will be covered.

We introduce a robust classification method based on the Bayesian predictive distribution (Bayesian Predictive Classification, referred to as BPC) for speech recognition. We and others have recently proposed a total Bayesian framework named Variational Bayesian Estimation and Clustering for speech recognition (VBEC). VBEC includes the practical computation of approximate posterior distributions that are essential for BPC, based on variational Bayes (VB). BPC using VB posterior distributions (VB-BPC) provides an analytical solution for the predictive distribution as the Student's t-distribution, which can mitigate the over-training effects by marginalizing the model parameters of an output distribution. We address the sparse data problem in speech recognition, and show experimentally that VB-BPC is robust against data sparseness.

A wireless interface for stacked chips in System-in-a-Package is presented. The interface utilizes inductive coupling between metal inductors. S21 parameters of the inductive coupling are measured between chips stacked in face-up for the first time. Calculations from a theoretical model have good agreement with the measurements. A transceiver circuit for Non-Return-to-Zero signaling is developed to reduce power dissipation. The transceiver is implemented in a test chip fabricated in 0.35 µm CMOS and the chips are stacked in face-up. The chips communicate through the transceiver at 1.2 Gb/s/ch with 46 mW power dissipation at 3.3 V over 300 µm distance. A scaling scenario is derived based on the theoretical model and measurement results. It indicates that, if the communication distance is reduced to 13 µm in 70 nm CMOS, 34 Tbps/mm2 will be obtained.