A multi-port device is characterized using measurement results of a two-port Vector Network Analyzer (VNA) with four different structures. The loads used as terminations are open-, or short-circuited transmission lines (TLs), which are characterized along with Ground-Signal-Ground pads based on L-2L de-embedding method. A new characterization method for a four-port device is introduced along with its theory. The method is validated using simulation and measurement results. The characterized four-port device is a Crossing Transmission Line (CTL), mainly used for over-pass or under-pass of RF signals. Four measurement results are used to characterize the CTL. The S-parameter response of the CTL is found. To compare the results, reconstructed responses compared with the measurements. Results show good agreement between the measured and modeled results from 1 GHz to 110 GHz.

In this paper, a novel and simple one-port de-embedding technique has been applied to through-silicon-via (TSV) characterization and modeling. This method utilized pad, via, and line structures to extract the equivalent circuit model of TSV. The main advantage of this de-embedding method is that it can reduce the chip area to fabricate test element groups (TEGs) for measurements while keeping S-parameter measurement accuracies. We also analyzed the electrical characteristics of substrate coupling and TSV equivalent impedance. Our results shows good agreements between measurement data and the equivalent circuit model up to 20GHz.

In this paper, a systematic design of X-band (9–10 GHz) 40 W pulse-driven GaN HEMT power amplifier is presented. The design includes device evaluation, verification of designed matching circuits, and measurements of the designed power amplifier. Firstly, the optimum input and output impedances for the selected GaN HEMT chip from TriQuint Semiconductor Inc. are evaluated using load-pull measurement. The selected GaN HEMT shows extremely low optimum impedances, which are obtained using a pre-match load-pull method due to the limitation of the tuning impedance range of conventional impedance tuners. We propose a novel extraction of the optimum impedances with general pre-match circuits. The extracted optimum impedances are found to be close to those computed, using the large signal model supplied from TriQuint Semiconductor. Using the optimum impedances, the matching circuits of the power amplifier are designed employing the combined impedance transformer type based on EM co-simulation. The fabricated power amplifier has a size of 1517.8 mm2, an efficiency above 45%, power gain of 7.7–9.9 dB and output power of 47–44.8 dBm at 9–10 GHz with pulse width of 10 µsec and duty of 10%.

This paper presents the evaluation of the L-2L de-embedding method with misalignment of the contact position. The issues of misalignment of the contact position are investigated. The analysis of misalignment in the L-2L de-embedding procedure is performed. Two comparisons are carried out to verify the error of the L-2L de-embedding method. The calculation percent error in quality factor of the transmission line becomes up to 9.0%, while the transistor S-parameter error percentage becomes up to 21% at 60 GHz in the experimental results. The results show that the measurement errors, caused by the misalignment of the contact position, should be considered carefully.

This paper presents a precise characterization of high-frequency characteristics of intrinsic channel of FinFET. For the de-embedding of the parasitics attached to the source, drain and gate terminals, it proposes special calibration patterns which can place the reference surface just beside the intrinsic part of the FinFET. It compares the measured S parameter data up to 40 GHz with the device simulation and shows good matching. The experimental data of the through pattern also confirms the accuracy of the de-embedded parasitics and extracted intrinsic part of FinFET.

Accurate device models are very important for the design of high-frequency circuits. One of the factors degrading the accuracy of device models appears during the de-embedding procedure. Generally, to obtain device characteristics without parasitic elements such as pads, a de-embedding procedure is essential. However, some errors are introduced during this procedure, which degrades the accuracy of device models. In this paper, we demonstrate that such errors due to de-embedding are cancelled in cascade circuit design, meaning that cascade circuits can be designed without knowing the actual characteristics of devices. Because it is difficult to know the actual characteristics of devices at a high frequency, the cancellation of the de-embedding error is expected to improve the accuracy of device models at high frequencies. After giving a theoretical treatment of de-embedding error cancellation, we report the results of simulations and measurements performed for verification.

This paper proposes a de-embedding method for on-chip S-parameter measurements at mm-wave frequency. The proposed method uses only two transmission lines with different length. In the proposed method, a parasitic-component model extracted from two transmission lines can be used for de-embedding for other-type DUTs like transistor, capacitor, inductor, etc. The experimental results show that the error in characteristic impedance between the different-length transmission lines is less than 0.7% above 40 GHz. The extracted pad model is also shown.

An L-2L through-line de-embedding method has been verified up to millimeter wave frequency. The parasitics of the pad can be modeled from the L-2L through-line. Measurement results of the transmission lines and transistors can be de-embedded by subtracting the parasitic matrix of the pad. Therefore, the de-embedding patterns, which is used for modeling active and passive devices, decrease greatly and the chip area also decreases. A one-stage amplifier is firstly implemented for helping verifying the de-embedding results. After that a four-stage 60 GHz amplifier has been fabricated in CMOS 65 nm process. Experimental results show that the four-stage amplifier realizes an input matching better than -10.5 dB and an output matching better than -13 dB at 61 GHz. A small signal power gain of 16.4 dB and a 1 dB output compression point of 4.6 dBm are obtained with a DC current consumption of 128 mA from a 1.2 V power supply. The chip size is 1.5 mm 0.85 mm.

A flexible noise de-embedding method for on-wafer microwave measurements of silicon MOSFETs is presented in this study. We use the open, short, and thru dummy structures to subtract the parasitic effects from the probe pads and interconnects of a fixtured MOS transistor. The thru standard are used to extract the interconnect parameters for subtracting the interconnect parasitics in gate, drain, and source terminals of the MOSFET. The parasitics of the dangling leg in the source terminal are also modeled and taken into account in the noise de-embedding procedure. The MOS transistors and de-embedding dummy structures were fabricated in a standard CMOS process and characterized up to 20 GHz. Compared with the conventional de-embedding methods, the proposed technique is accurate and area-efficient.

In this paper, we propose an accurate and scalable S-parameter de-embedding method for RF/microwave on-wafer characterization of silicon MOSFETs. Based on cascade configurations, this method utilizes planar open, short, and thru standards to estimate the effects of surrounding parasitic networks on a MOS transistor. The bulk-shielded open and short standards are used to simulate and de-embed the probe-pad parasitics. The thru standard are used to extract the interconnect parameters for subtracting the interconnect parasitics in gate and drain terminals of the MOSFET. To further eliminate the parasitics of dangling leg in source terminal of the MOSFET, we also introduce the microwave and multi-port network analysis to accomplish the two-port-to-three-port transformation for S-parameters. The MOSFET and its corresponding de-embedding standards were fabricated in a standard CMOS process and characterized up to 40 GHz. The scalability of the open, short, and thru standards is demonstrated and the performance of the proposed de-embedding procedure is validated by comparison with several de-embedding techniques.

A de-embedding technique for the measurement of very small parasitic capacitances of package or small module interconnects is presented. At high frequencies small parasitic capacitances become important, and measurement probes can strongly affect measurement results. The present technique is based on additional measurements with only one tip of the probe touching one conductor, while the second tip is kept floating on the substrate. A necessary condition for its application is that the measured capacitance does not depend on the position of the floating probe tip. Measurements with inverted probe tip polarities are also used. In this way, the capacitances between probe tips and DUT can be estimated together with the parasitic capacitances of interest. Depending on the required accuracy, de-embedding of different orders have been introduced, which consider capacitance configurations of increasing complexity. The technique requires the solution of one or more systems of non-linear equations. In the present example the minimization of the norm of the residual of the system has been treated as a least squares problem, and has been solved numerically with MATLAB. The accuracy of the measurement can be also approximately estimated with the residual. As application example, a small module with power and ground planes has been considered. Two different probes have been used. Even though the stray capacitances of the probes are very different, the values of the extracted parasitic capacitances are in agreement with each other. The accuracy has been verified also with simulation results. To this purpose, a combination of known formulas from the literature, a 2D Finite Element Method (FEM) tool and a 3D Boundary Element Method (BEM) tool have been used. A high accuracy can be obtained, even when a strong capacitive coupling between probe ground and DUT is present. The technique can be applied also when only a subset of measurement results are available.

In this study, a cascade open-short-thru (COST) de-embedding procedure is proposed for the first time for on-wafer device characterization in the RF/microwave frequency regime. This technique utilizes the "open" and "short" dummy structures to de-embed the probe-pad parasitics of a device-under-test (DUT). Furthermore, to accurately estimate the input/output interconnect parasitics, including the resistive, inductive, capacitive, and conductive components, the "thru" dummy device has been characterized after probe-pad de-embedding. With the combination of transmission-line theory and cascade-configuration concept, this method can efficiently generate the scalable and repeatable interconnect parameters to completely eliminate the redundant parasitics of the active/passive DUTs of various device sizes and interconnect dimensions. Consequently, this method is very suitable for the on-wafer automatic measurement.

A simple adapter de-embedding method is presented in a six-port calibration process using only one sliding load and one standard short. Adapter de-embedding is performed to extract the S-parameters of the adapter from the six-port system parameters. The concept of this method is based on the relations between the S-parameters and the Fourier coefficients of the periodic return loss of the adapter. To complete the de-embedding procedure, there are two measurement steps: one is return loss measurement with the sliding load, and the other, sidearm power measurement with the standard short. Using these measured values, unique solutions of the S-parameters are determined. A computer-controlled six-port with 2.4 mm coaxial-type connector was designed for calibration using a waveguide-type sliding load over the frequency range of 8.5-12.0 GHz. Through experiments, the adapter for joining two unlike connector types was measured. Then the reflection coefficients of the adapter with the sliding load measured by the calibrated six-port and those calculated from the S-parameters were compared with each other. As a result, an overall good agreement with standard deviation of less than 0.1% was found at all setting frequencies. One of the main features of the method is that the S-prameters of a two-port as well as the system parameters of a six-port can be determined by means of simple scalar measurement.