We propose an integrated smart cable operation system and its architecture for the future cable network. In the proposed architecture, an application programs and various modules are loosely coupled using a cable operation system platform. We anticipate the task flows for the future optical cable network operation in order to realize the proposed system and architecture. Each task flow is broken down into "atomic tasks." The task flow can be changed easily by combining these atomic tasks. We use an object-oriented design for designing the cable operation system platform. As a first step towards the construction of the proposed system a pre-prototype system was constructed and the results are shown.

This paper presents an optimal constraint graph generation algorithm for graph-based one-dimensional layout compaction. The first published algorithm for this problem was the shadow-propagation algorithm. However, without sophisticated implementation of a shadow-front, complexity of the algorithm could fall into O(n2), where n is the number of layout objects. Although our algorithm, called the enhanced plane-sweep based graph generation algorithm, is an extension of the shadow-propagation algorithm, such a drawback is resolved by introducing an enhanced plane-sweep technique. The algorithm maintains multiple shadow-fronts simultaneously by storing them in a work-list called previous-boundary. Since a balanced search tree is selected for implementation of the worklist, total complexity of the algorithm is O(n log n) which is optimal. Experimental results show that the enhanced plane-sweep based graph generation algorithm runs in almost linear time with respect to the number of layout objects and is faster than the perpendicular plane-sweep algorithm which is also optimal in terms of time complexity.

In this paper, a methodology for designing the architecture of the processor array for wide class of image processing algorithms is proposed. A concept of spatially expanding the SFG description which enables us to handle the problem as merely one-dimensional signal processing is used in constructing the methodology. Problem of I/O interface which is critical in real-time processing is also considered.

The Memory-Based Reasoning (MBR) is one of the mainstay approaches in massively parallel artificial intelligence research. However, it has not been explored from the viewpoint of hardware implementation. This paper demonstrates high robustness of the MBR, which is suitable for hardware implementation using Wafer Scale Integration (WSI) technology, and proposes a design of WSI-MBR hardware. The robustness is evaluated by a newly developed WSI-MBR simulator in the English pronunciation reasoning task, generally known as MBRTalk. The results show that defects or other fluctuations of device parameters have only minor impacts on the performances of the WSI-MBR. Moreover, it is found that in order to get higher reasoning accuracy, the size of the MBR database is much more crucial than the computation resolution. These features are proved to be caused by the fact that MBR does not rely upon each single data unit but upon a bulk data set. Robustness in the other MBR tasks can be evaluated in the same manner as discussed in this paper. The proposed WSI-MBR processor takes advantage of benefits discovered in the simulation results. The most area-demanding circuits--that is, multipliers and adders--are designed by analog circuits. It is expected that the 1.7 million processors will be integrated onto the 8-inch silicon wafer by the 0.3 µm SRAM technology.

This paper describes an automatic transistor model parameter generation technique for a circuit simulator which can take device geometry into account. An 'area factor' is used to generate model parameters for different transistor shapes; however, the conventional method could not reflect the actual geometry differences other than for the emitter area. This resulted in inaccurate model parameters and such parameters were not acceptable to accurately simulate circuits for RF ICs. The proposed technique uses actually measured parameters and process data for a reference transistor and generates the individual model parameters for different shape transistors. In this technique, the parasitic resistor values are calculated and fitted in place of directly extracting them from the measured data. This ensures a better estimate. The reference transistor is made sufficiently large to neglect measurement errors in generating the parasitic capacitors. Thus, the model parameters for a very small transistor can be generated accurately. The model generating procedure has been implemented as a pre-processor to SPICE. This technique enables a fast turn around for RF IC circuit design which uses various shape transistors.

The objective of this work is to demonstrate a new hierarchical timing analysis technique for multi-phase clocked designs with feedback loops including level sensitive latches. By using this technique, large synchronous designs can be analyzed accurately without loop breaking.

A location registration/paging procedure which is free from location registration area design is proposed. Each base station (BS) broadcasts a "responsibility area", composed of its own and neighboring cells' identification (ID). A mobile station (MS) makes a new location registration request when the current BS's responsibility area does not include the MS's registered location. Each BS is allowed to decide its own responsibility area autonomously based on route information, which is composed of neighboring cells' ID and reported from MSs. Therefore, the responsibility area can be adaptively changed based on MSs' moving characteristics. Moreover, this procedure solves the problems of registration traffic concentration and excess registration request on boundary BSs.

The self-checking design using 2-rail logic is one of the most popular design of self-shecking circuits. Even for a self-checking circuit, a test is necessary after VLSI chip or system fabrication, at each time the system is powered, and, under certain circumstances, in the case of maintenance. Therefore, an easy test scheme is desirable for that circuit. A new design method for a 2-rail logic combinational circuit is proposed, where stuck-open and sutck-on faults FETs can be easily detected. In the proposed circuit design, 4 FETs are added to each gate in a conventional 2-rail logic circuit. Two logical gates, DOR and DAND, are also added to the circuit as fault observing gates. Each test consists of a sequence of 3 input vectors, that is, a type of 3-pattern test, ti1ti2ti3. A test can be easily generated and fault observation is easy. Stuck-at fault and stuck-open fault on lines and almost all multiple faults can also be detected by the test. A gate construction method, test generation method, circuit construction method, and several discussions including gate delay increasing are presented.

This paper describes MENDELS ZONE, a Petri-net-based concurrent programming environment, which is especially suitable for cooperating discrete event systems. MENDELS ZONE adopts MENDEL net, which is a type of high level (hierarchical colored) Petri net. One of the characteristics of the MENDEL nets is a process-oriented hierarchy like CCS, which is different from the subnet-oriented hierarchy in the Jensen's hierarchical colored Petri net. In a process-oriented hierarchy, a hierarchical unit is a process, which is more natural for cooperating and decentralized discrete event control systems. This paper also proposes a design methodology for MENDEL nets. Although many Petri net tools have been proposed, most tools support only drawing, simulation, and analysis of Petri nets; few tools support the design methodology for Petri nets. While Petri nets are good final design documents easy to understand, analyzable, and executable it is often difficult to write Petri nets directly in an earlier design phase when the system structure is obscure. A proposed design methodology makes a designer to construct MENDEL nets systematically using causality matrices and temporal logic. Furthemore, constructed MENDEL nets can be automatically compiled into a concurrent programming language and executed on a parallel computer.

The paper proposes a combined delay model to manipulate the variance of the delay time of logic elements and a new timing verification method based on the theory of regular expressions. With the delay time of logic elements such as TTL SN7400, the minimum delay time (dm), the maximum delay time (dM), and the typical delay time are specified in the manual, and the delay time of an element is one in the interval between dm and dM. Here we assume a discrete time, and we manipulate the variance of the delay time as a set of output strings corresponding to each delay time. We call the model as the combined delay model. Since many output strings are generated with a single input string, the usual timing simulation method cannot be applied. We propose a timing verification method using a behavior extraction method of logic circuits with respect to a time string set: with respect to the specified input set, the method extracts the output string set of each element in the circuit. We devised (1) a mechanism to keep the correspondence between a primary input string and an output string with respect to the primary input string, (2) a mechanism to manipulate the nondeterminism included in the combined delay model, and (3) an event-driven like data compaction method in representing finite automata. We focused on the hazard detection problem and the verification of asynchronous circuits, and show the effectiveness of our method with medium sized circuit with 100 elements or so. The method includes the state explosion, but the data compaction method and the extraction for only the specified input set are useful to control the state explosion.

In recent VLSI design of digital data paths, significantly more area is occupied by interconnect elements than by functional units and registers. Nevertheless, until recently most work in data path synthesis has been concentrated on trying to reduce the area of functional units and registers, without paying much attention to the interconnect area. Lately, research that addresses reducing the area of interconnection and of functional units and registers is increasing, but in them, most algorithms for assigning interconnect elements are not efficient enough to optimize the interconnect area. In most current research, algorithms for interconnect element assignment are used to calculate the cost functions during the scheduling and/or allocation steps. This makes it impossible to use efficient optimization algorithms that may consume long time. This paper presents some new algorithms used to assign interconnect elements in data paths. The algorithms minimize the number of multiplexer inputs after the scheduling and operator/register allocations have been made. The algorithms have two characteristics. First, we use a branch and bound method for small problems. We confirmed that exact solutions in practical time can be obtained with this method for rather large problems, when the solutions are restricted to a one-level multiplexer model. Second, we use a certain heuristic method for larger problems. The algorithms have been implemented in C on an Apollo Domain Series 10000.

This paper deals with the sub-problems of generating a mask pattern from the logical description of a large-scale CMOS circuit. The large-scale layout can be generated in divide-and-conquer style: divide a given circuit into a set of sub-circuits, generate the layout of each sub-circuit, and merge the resulting layouts to create the whole layout. This paper proposes a layout synthesis algorithm for a sub-circuit with physical constraints for the synthesis scheme above. The physical constraints considered here are the relative placement of logic cells (sets of logic gates) and the routing constraint based on the costs of wiring layers and vias. These constraints will be given by the global optimizer in a two-dimensional layout synthesis routine, and they should be kept at the subsequent one-dimensional layout synthesis for a sub-circuit. The latter is also given for enhancing the circuit performance by limiting the usage of wiring layers and vias for special net such as a clock net. The placement constraint is maintained using PQ-tree, a tree structure representing a set of restricted permutations of elements. One-dimensional layout synthesis determines the placement of transistors by the enhanced pairwise exchanging method under the PQ-tree representation. The routing constraints is considered in the newly developed line-search routing method using a cost-based searching. Experimental results for practical standard cells, including up to 200 transistors, prove that the algorithms can produce the layouts comparable to handcrafted cells. Also on a two-dimensional layout synthesis using the algorithms, the results for benchmark circuits of Physical Design Workshop 1989, i.e., MCNC benchmark circuits, are superior to the best results exhibited at Design Automation Conference 1990.

Net-Oriented Analysis and Design (NOAD) is defined as three items: (1) Various nets are utilized as an effective modeling method. (2) Inter-relationships among verious nets are determined. (3) Verification or analysis methods for nets are provided and they are implemented based on the mathematical theory, that is Net theory. Very few methods have been presented to satisfy these three items. For example, the Real-Time SA method covers item (1) only. The Object-Oriented Analysis and Design method (OOA/OOD) covers items (1) and (2). NOAD can be regarded as an extension to OOA/OOD. This paper discusses how effectively various nets have been used in actual software development support metnods and tools and evaluates such several methods and tools from the NOAD viewpoint.

A design system for a special purpose processor executing algorithms described by high level language is discussed. The system can generate an optimized architecture for the processor and also supply a specialized high level language compiler for the processor. A new optimization procedure is introduced to find effective functional blocks that can contribute to the improvement of performance. Functional blocks are found by simulation of the frequently appearing patterns of execution in the algorithm and used to yield a useful combined instruction.

Recently, Burch et al. proposed symbolic model checking method to verify sequential machines formally. The method, which is based on logic function manipulation using binary decision diagram, can handle large sequential machines that cannot be handled by the conventional techniques. The expressive power of Computational Tree Logic (CTL), which was used by Burch et al., is not very powerful, for example, CTL cannot describe repetition of events. This papers shows an extension of the symbolic model checking algorithm to Branching time regular temporal logic (BRTL), which has been proposed by the authors as an improvement of CTL in terms of expressive power. The implemented verifier based on the proposed algorithm could verify behaviors of a microprocessor composed of approximately 1,600 gates and 68 flipflops.

Telecommunication services are accomplished by cooperative networks of widely distributed communication processes and service users. Those specifications are often modeled by a set of possible message sequences among cooperating processes and users. The distributed and cooperative nature of telecommunication services results in a wide variety of message sequences and makes it more difficult for service designers to design such telecommunication services. To mitigate the difficulty, we propose a design support system with MSRs (message sequence rules) as design knowledge. The system supports the following two design activities: (1) specification of a typical message sequence that corresponds to a service behavior in a successful case, and (2) specification of incidentally possible message sequences that involve service behaviors in successful and unsuccessful cases. For the former activity, the system interacts with designers and identifies the messages they give with MSRs to understand the context of the message sequence and suggest possible subsequent messages. For the latter activity, the system applies MSRs to the typical message sequence and reasons possible messages from/to relevant processes and users under every state to suggest incidentally possible message sequences. Accordingly, designers may be relieved of investigating a wide variety of service behaviors in successful and unsuccessful cases. The system capability is based on MSRs equivalent to reusable message sequence components. MSRs can be obtained through abstraction of implementation-dependent messages and decomposition of those sequences into temporal relations among messages. The rule acquisition method provides MSRs with the potential to generate a wide variety of message sequences. In order to verify rule applicability, we have experimentally designed three kinds of services and conducted an experimental rule application to those specifications. The experimental evaluation results indicate that applicability is fairly high.

A 1/2 frequency divider using resonant-tunneling hot electron transistors (RHETs) has been proposed and demonstrated. The circuit make the best use of negative differential conductance, a feature of RHETs, and contains one half transistors than used in conventional circuits. The RHETs were fabricated using self-aligned InGaAs RHETs and WSiN thin-film resistors on a single chip. The RHETs have an i-InGaAlAs/i-InGaAs collector barrier that improves the current gain at low collector-base voltages. Circuit operation was confirmed at 77 K.

This paper proposes design schemes which obtain an efficient spare-channel assignment against single and double link failures for a self-healing network. Spare-channel design problems can be formulated as a linear-programming (LP) problem when variables are assumed to be continuous. For the problem, the proposed algorithm effectively solves a sub-set of whole constraints by making use of a maximum-flow algorithm in an iterative manner. It is shown that the maximum number of iteration times is limited by the number of links in the network. Moreover, the relation between the design function and the self-healing function is discussed. It is also shown that the cooperation of the two functions can realize more effective control in large scale networks.

Syntax-directed editors have several advantages in editing programs because programming is guided by the syntax and free from syntax errors. Nevertheless, they are less popular than text editiors. One of the reason is that they force a priori specified editing structures on the user and do not allow him to use his own structure. ACE (Algorithmically Customizable syntax-directed Editor) provides a solution for this problem by using a technique of machine learning; ACE has a special function of customizing the grammar algorithmically and interactively based on the learning method for grammars from examples and queries. The grammar used in the editor is customized through interaction with the user so that the user can edit his program in a more familiar structure. The customizing function has been implemented based on the methods for learning of context-free grammars from structural examples, for which the correctness and the efficiency are proved formally. This guarantees the soundness and the efficiency of customization. Furthermore, ACE can be used as an algorithmic and interactive tool to design grammars, which is required for several purposes such as compiler design and pretty-printer design.

Based on the Fornasini-Marchesini second model, an efficient algorithm is developed to derive the characteristic polynomial and the inverse of the system matrix from the state-space parameters. As a result, the external description of the Fornasini-Marchesini second model is clarified. A technique for designing 2-D recursive digital filters in the frequency domain is then presented by using the Fornasini-Marchesini second model. The resulting filter approximates both magnitude and group delay specifications and its stability is always guaranteed. Finally, three design examples are given to illustrate the utility of the proposed technique.