A key element in the CDMA transmission is DS spreading. Spreading in a DS/SSMA system are provided in two categories-synchronization and data. For synchronization sequences, good auto-correlation and cross-correlation properties are required in order to guarantee fast acquistion with a minimum false alarm probability. On the other hand, the auto-correlation property may not be so important in data spreading since synchronization is obtained by synchronization spreading. In this paper we provide a set of synchronization sequences and a set of data sequences--each a set of binary N-tuples--that have the necessary correlation constraints.

This paper describes an exact symbolic formulation of resource-constrained scheduling which allows speculative operation execution in arbitrary forward-branching control/data paths. The technique provides a closed-form solution set in which all satisfying schedules are encapsulated in a compressed OBDD-based representation. An iterative construction method is presented along with benchmark results. The experiments demonstrate the ability of the proposed technique to efficiently extract parallelism not explicitly specified in the input description.

We present a design chart and a manufacturing process for mm-wave absorber consisting of two spacers (poly-carbonate) and two-resistive sheets (polyethylene terephthalate deposited with Indium Tin Oxide). The conventional design chart gives us necessary information to make a desirable absorber. Based on the design chart, a multi-layered type absorber was manufactured and it is concluded that a significant absorption level (-20dB) is attained at a wide-frequency range of 46-66GHz.

This paper proposes a large capacity high-speed file memory system implemented with wafer scale RAM which adopts a novel defect-tolerant technique. Based on set-associative mapping, the defective memory blocks on the wafer are repaired by switching with the spare memory blocks. In order to repair the clustered defective blocks, these are permuted logically with other blocks by adding some constant value to the input block addresses. The defective blocks remaining even after applying the above two methods are repaired by using error control codes which correct soft errors induced by alpha particles in an on-line operation as well as hard errors induced by the remaining defective blocks. By using the proposed technique, this paper demonstrates a large capacity high-speed WSI file memory system implemented with high fabrication yield and low redundancy rate.

This paper proposes a new approach for the development of a module generator that can parameterize both the size and the structure of layout. The proposed method acquires a design procedure from the design process of a designer, and reuses it to synthesize new layouts with different input parameters that affect the size or the structure of layout. In this method, a designer creates a module layout on a layout editor instead of writing a program. From his design process, a procedure to synthesize the layout is automatically derived. Then, it is generalized so that it could be valid under different values of input parameters. The generalized procedure is independent of design rules, and is capable of synthesizing error-free module layouts of different size and structure. Also, the procedure includes designer's requirements on how the layout should be designed. The experimental results of applying the approach for developing generators of analog device components show effectiveness of our approach.

In this paper, a design of TCM signals for Middleton's class-A impulsive noise environment is investigated. The error event characteristics under the impulsive noise is investigated, and it is shown that the length of the signal sequence is more important than Euclidean distance between the signal sequences. Following this fact, we introduce the shortest error event path length as a measure of the signal design. In order to make this value large, increasing of states of convolutional codes is employed, and the performance improvement achieved by this method is evaluated. Numerical results show the great improvement of the error performance and conclude that the shortest error event path length is a good measure in the design of TCM signals under impulsive noise environment. Moreover, the capacity of class-A impulsive noise channel is evaluated, and the required signal sets expansion rates to obtain the achievable coding gain is discussed.

A simple method is presented to calculate the parasitic capacitance effect in the propagation delay of series-connected MOS (SCM) structures. This method divides SCM circuits into two parts and accurately calculates the contribution of each part to the difference from the delay without parasitic capacitances.

Technology mapping algorithms for LUT (Look Up Table) based FPGAs have been proposed to transfer a Boolean network into logic-blocks. However, since those algorithms take no layout information into account, they do not always lead to excellent results. In this paper, a simultaneous technology mapping, placement and global routing algorithm for FPGAs, Maple, is presented. Maple is an extended version of a simultaneous placement and global routing algorithm for FPGAs, which is based on recursive partition of layout regions and block sets. Maple inherits its basic process and executes the technology mapping simultaneously in each recursive process. Therefore, the mapping can be done with the placement and global routing information. Experimental results for some benchmark circuits demonstrate its efficiency and effectiveness.

A single-chip architecture for three-dimensional (3-D) computer graphics (CG) is discussed assuming portable equipment with a 3-D CG interface. Based on a discussion of chip requirements, an architecture utilizing DRAM technology is proposed. A 31-Mbit, on-chip DRAM cell array allows a full-color, 480640-pixel frame with two 3-D frame buffers for double buffering and one 2-D frame buffer for superimposed or background images. The on-chip pixel generator produces R, G, B, and Z data in a triangular polygon with a zigzag-scan interpolation algorithm. The on-chip frame synthesizer combines data from one of the 3-D buffers with that from the 2-D buffer to produce superimposed or background 2-D images within a 3-D CG image. Parallel alpha-blending and Z-comparison circuits attached to the DRAM cell array provide a high data I/O rate. Estimation of the chip performance assuming the 0.35-µm CMOS design rule shows the chip size, the drawing speed, on-chip data I/O rate, and power dissipation would be 1413.5-mm, 0.25 million polygons/s, 1 gigabyte/s, and 590 mW at a voltage of 3.3 V, respectively. Based on circuit simulations, the chip can run on a 1.5-V dry cell with a drawing speed of 0.125 million polygons/s and a power dissipation of 61 mW. A scaled-down version of the chip which has an 1-kbit DRAM cell array with an attached alpha-blending circuit is being fabricated for evaluation.

This paper presents a method, called reduced scan shift, which generates short test sequences for full scan circuits. In this method, scan shift operations can be reduced, i.e., not all but part of flip-flops (FFs) are controlled and observed. This method, unlike partial scan methods, does not decrease fault coverage. In the reduced scan shift, test vectors for the combinational part of a circuit are fistly generated. Since short test sequence will be obtained from the small test vectors set, test compaction techniques are used in the test vector generation. For each test vector in the obtained test set, it is found which FFs should be controlled or observed. And then a scan chain is configured so that FFs more frequently required to be controlled (observed) can be located close to the scan input (output). After the scan chain is configured, the scan shift requirement is examined for the essential faults of each test vector. Essential fault is defined to be a fault which is detected by only one test vector but not other test vectors. The order of test vectors is carefully determined by comparing the scan control requirement of a test vector with the scan observation requirement of another test vector so that unnecessary scan shift operations only for controlling or observing FFs can be reduced. A method of determining the order of test vectors with state transition is additionally described. The effectiveness of the proposed method is shown by the experimental results for benchmark circuits.

This paper proposes a new environment for high-level VLSI design specification validation using "Algorithmic Debugging" and evaluates its benefits on three significant examples (a protocol processor, an 8-bit CPU, and a Prolog processor). A design is specified at a high-level using the structured analysis (SA) method, which is useful for analyzing and understanding the functionality to be realized. The specification written in SA is transformed into a logic programming language and is simulated in it. The errors (which terminate with an incorrect output in the simulation) included in the three large examples are efficiently located by answering junt a few queries from the algorithmic debugger. The number of interactions between the designer and the debugger is reduced by a factor of ten to a hundred compared to conventional simulation based validation methodologies. The correct SA specification can be automatically translated into a Register Transfer Level (RTL) specification suitable for logic synthesis. In this environment, a designer is freed from the tedious task of debugging a RTL specification, and can concentrate on the design itself. This environment promises to be an important step towards efficient high-level VLSI design specification validation.

Along with the improvement of micro processors and local area networks, a distributed system becomes useful to realize a telecommunication system. It has potential advantage to achieve both high performance and high reliability. However, the design of a distributed system tends to be more complicated compared to a conventional centralized system. For the purpose of the standardization of distributed processing, ISO and ITU-T study the Open Distributed Processing (ODP) and are currently standardizing the Basic Reference Model of ODP (RM-ODP). To avoid dealing with the complexity of distributed systems, RM-ODP defines five viewpoints. The viewpoint approach of RM-ODP is proposed as a framework for the design of a distributed system. Although some previous works give the design methods of distributed systems based on the ODP viewpoint approach, the detailed design method has not been fully specified or all of the five viewpoints are not taken into account. In this paper, we describe a detailed design method for a distributed telecommunication system based on the ODP viewpoint approach. The method applies the five viewpoints to the three phases of design of a distributed system, that is, requirement analysis, functional design and detailed design phase. It clarifies what specifications for the target system should be made from the individual viewpoints and how the specifications are related each other. It also takes account of the platform which provides the distribution support, and gives the design method for both the platform and the application specific functions on the platform. The design method is examined by applying it to the design of a distributed MHS system supporting X.400 series protocols. In this example, the remote procedure call based on the client-server model is selected as the base of the platform. The result shows that our method is useful to simplify the complexity of the design for a distributed telecommunication system.

This paper proposes a methodology for fine evaluation of the uncertain behaviors of systems affected by any fluctuation of internal structures and internal parameters, by the use of a new concept on the fuzzy mapping. For a uniformly convex real Banach space X and Y, a fuzzy mapping G is introduced as the operator by which we can define a bounded closed compact fuzzy set G(x,y) for any (x,y)∈X×Y. An original system is represented by a completely continuous operator f defined on X, for instance, in a form xλ(f(x)) by a continuous operator λ: YX. The nondeterministic fluctuations induced into the original system are represented by a generalized form of the fuzzy mapping equation xGβ (x,f(x)) {ζX|µG(x,f(x))(ζ)β}, in order to give a fine evaluation of the solutions with respect to an arbitrarily–specified β–level. By establishing a useful fixed point theorem, the existence and evaluation problems of the "β–level-likely" solutions are discussed for this fuzzy mapping equaion. The theory developed here for the fluctuation problems is applied to the fine estimation of not only the uncertain behaviors of system–fluctuations but also the validity of system–models and -simulations with uncertain properties.

The concept of flexible system is long being used by many researchers, aiming to solve some particular problem of adaptation. The problem is viewed differently in different situations. In this paper, we first give a set of definitions and specifications to generalize this concept applicable to any system and in particular to communication networks. Through these definitions we will formalize, what are the conditions a system should satisfy to be called as a Flexible Communication System. The rest of the paper we formalize the concepts of flexible information network, and propose an agent oriented architecture that can realize it.

By addressing design requirements for multicast ATM switching, this paper attempts to provide an integrated view of modular and expandable switch architectures suitable for both unicast and multicast switching for future B-ISDNs. Several large and modular multicast ATM switching architectures are discussed, each of which handles different traffic situations. These architectures consist of multiple shared-buffer copy network modules of adequate size suitable for fabrication on a single chip, and small output memory switch modules. A new modular link-grouped multistage interconnection network is proposed for interconnecting copy network modules and memory switch modules, so that future large multicast ATM switching networks can be built in a modular fashion. The described modular architectures can significantly facilitate signal synchronization in large-scale switching networks.

The design theory was revealed by theoretical analysis of the measuring apparatus, and was confirmed experimentally. Higher quality tags having new circuit disigns were proposed by the revealed theory. The measuring apparatus equivalent to the security system was produced to estimate the properties of the LC resonant circuit security tags quantitatively.

This paper describes a procedural detailed compaction method for the symbolic layout design of CMOS leaf cells and its algorithmic aspects. Simple symbolic representations that are loosely designed by users in advance are automatically converted into densely compacted physical patterns in two phases: symbolic–to–pattern conversion and segment–based detailed compaction. Both phases are executed using user-defined procedures and a specified set of design rules. The detailed compaction utilizes a segment–based constraint graph generated by an extended plane sweep method where various kinds of design rules can be applied. Since various kinds of basic operations can be applied to the individual segments of patterns in the procedures, the detailed procedure for processing can be described in accordance with fabrication process technologies and the corresponding sets of design rules. This combined stepwise procedure provides a highly flexible framework for the symbolic layout of CMOS leaf cells. The proposed approach was implemented in a symbolic layout system called CAMEL. To date, more than 300 kinds of symbolic representations of CMOS leaf cells have been designed and are stored in the database. Using several different sets of design rules, symbolic representations have been automatically converted into compacted patterns without design rule violations. The areas of those generated patterns were averaged at 98% of the manually designed patterns. Even in the worst case, the increases in area were less than about 10% of the manually designed ones. Furthermore, since processing times are much shorter than manual design periods, for example, 300 kinds of symbolic representations can be converted to corresponding physical patterns in only a day. It is evident, through these practical design experiences with CAMEL, that our approach is more flexible and process–tolerant than conventional ones.

In this paper, the power dissipation issue is considered in the gate sizing procedure. In order to observe the tradeoff among area, delar and power dissipation in a circuit, gate sizing algorithms which can minimize power under delay constraints or minimize area under power and delay constraints are formulated. Experiments are performed to investigate the properties of area–power–delay tradeoff in the gate sizing procedure.

This paper describes a preconstrained compaction method and its application to the direct design-rule conversion of CMOS layouts. This approach can convert already designed physical patterns into compacted layouts that satisfy user-specified design rules. Furthermore, preconstrained compaction can eliminate unnecessarily extended diffusion areas and polysilicon wires which tend to be created with conventional longest path based compactions. Preconstrained compaction can be constructed by combining a longest path algorithm with forward and backward slack processes and a preconstraint generation process. This contrasts with previously proposed approaches based on longest path algorithms followed by iterative improvement processes, which include applications of linear programming. The layout styles in those approaches are usually limited to a model where fixed-shaped rectilinear blocks are moved so as to minimize the total length of rectilinear interconnections among the blocks. However, preconstrained compaction can be applied to reshaping polygonal patterns such as diffusion and channel areas. Thus, this compaction method makes it possible to reuse CMOS leaf and macro cell layouts even if design rules change. The proposed preconstrained compaction approach has been applied to direct design-rule conversion from 0.8-µm to 0.5-µm rules of CMOS layouts containing from several to 10,195 transistors. Experimental results demonstrate that a 10.6% reduction in diffusion areas can be achieved without unnecessary extensions of polysilicon wires with a 39% increase in processing times compared with conventional approaches.

Kalman filter is an essential tool in signal processing, modern control and communications. The filter estimates the states of a given system from noisy measurements, using a mean-square error criterion. Although Kalman filter has been shown to be very versatile, it has always been computationally intensive since a great number of matrix computations must be performed at each iteration. Thus the exploitation of this technique in broadband real time applications is restricted. The solution to these limitations appears to be in VLSI (very large scale integration) architectures for the parallel processing of data, in the form of systolic architectures. Systolic arrays are networks of simple processing cells connected only to their nearest neighbors. Each cell consists of some simple logic and has a small amount of local memory. Overall data flows through the array are synchronously controlled by a single main clock pulse. In parallel with the development of Kalman filter, the square root covariance and the square root information methods have been studied in the past. These square root methods are reported to be more accurate, stable and efficient than the original algorithm presented by Kalman. However it is known that standard SRIF is less efficient than the other algorithms, simply because standard SRIF has additional matrix inversion computation and matrix multiplication which are difficult to implement in terms of speed and accuracy. To solve this problem, we use the modified Faddeeva algorithm in computing matrix inversion and matrix multiplication. The proposed algorithm avoids the direct matrix inversion computation and matrix multiplication, and performs these matrix manipulations by Gauss elimination. To evaluate the proposed method, we constructed an efficient systolic architecture for standard SRIF using the COMPASS design tools. Actual VLSI design and its simulation are done on the circuits of four type processors that perform Gauss elimination and the modified Givens rotation.