This paper concerns optimized facility design for VLSI production. The methods proposed are applicable in planning LSI production facilities with a good balance between the number of machines and the number of operators. The sequence in each processing step is analyzed in detail. A new algorithm based on the queueing model is developed for estimating the simultaneous requirements for the two kinds of resources, machines and operators. This estimation system can be applied to complicated fabrication schemes, such as batch processing, continuous processing, and mixed technologies. This methodology yields guidelines for ASIC LSI production system design.

In this paper, we show that the conventional BCH codes can be better than the AG codes when the number of check symbols is relatively small. More precisely, we consider an AG code on Cab whose number of check symbols is less than min {g+a, n-g}, where n and g denote the code length and the genus of the curve, respectively. It is shown that there always exists an extended BCH code, (i) which has the same designed distance as the Feng-Rao designed distance of the AG code and the code length and the rate greater than those of the AG code, or (ii) which has the same number of check symbols as that of the AG code, the designed distance not less than that of the AG code and the code length longer than that of the AG code.

Fundamental microwave key devices used in achieving compact mobile/portable telephones (raidio units) are discussed. The historical development flow of the systems and radio units are introduced, with respect to the 800-/900-MHz and 1.5-GHz Japanese cellular radio systems. The design concept of the developed radio units is briefly described. Tehnical requirements for RF circuits are reviewed and the developed key devices are practically applied to the circuits. Key factors in the requirements are also shown. Finally. future trends fro the key devices are surveyed from the stand point of achieving a smaller and more light weight pocket radio unit.

A new global method for constructing a C2 piecewise quartic polynomial curve is presented. The coefficient matrix of equations which must be solved to construct the curve is tridiagonal. The joining points of adjacent curve segments are the given data points. The constructed curve reproduces exactly a polynomial of degree four or less. The results of experiments to test the efficiency of the new method are also shown.

AlGaAs/GaAs power HBTs for digital cellular phones have been developed. A three-dimensional thermal analysis taking the local-temperature dependence of the collector current into account was applied to the thermal design of the HBTs. The HBTs were fabricated using the hetero-guardring fully selfaligned transistor technique. The HBT with 220µm2 60 emitters produced a 31.7 dBm CW-output power and 46% poweradded efficiency with an adjacent channel leakage power of -49 dBc at the 50kHz offset bands for a 948 MHz π/4-shifted QPSK modulated signal at a low collector-emitter voltage of 3V. Through comparison with the conventional GaAs power FETs, it has been shown that AlGaAs/GaAs power HBTs have a great advantage in reducing the chip size.

In the business systems design learning environment, there may be more than one solution to any given problem. For instance, the data model will be different depending on each learner's perspective. Accordingly, group learning systems are very effective in this domain. We have developed CAMELOT (Collaborative and Multimedia Environment for Learners on Teams) [18] using the Nominal Group Technique for group problem solving. In this paper, the basic framework of the collaborative learning system and the effectiveness of collaborative learning in designing the Data Model are described. By using CAMELOT, each learner learns how to analyze through case studies and how to cooperate with his or her group in problem solving. Learners come to a deeper understanding from using CAMELOT than from studying independently because they are enabled to reach better solutions through discussion, tips from other learners, and examination of one another's works.

A speedup of Lenstra's Elliptic Curve Method of factorization is presented. The speedup works for integers of the form N = PQ2, where P is a prime sufficiently smaller than Q. The result is of interest to cryptographers, since integers with secret factorization of this form are being used in digital signatures. The algorithm makes use of what we call Jacobi signatures. We believe these to be of independent interest.

This paper presents a combinatiorial characterization of broadcast authentication in which a transmitter broadcasts v messages e1(s), , ev(s) to authenticate a source state s to all n receivers so that any k receivers cannot cheat any other receivers, where ei is a key. Suppose that each receiver has l keys. First, we prove that k < l if v < n. Then we show an upper bound of n such that n v(v - 1)/l(l - 1) for k = l - 1 and n /+ for k < l - 1. Further, a scheme for k = 1 - 1 which meets the upper bound is presented by using a BIBD and a scheme for k < l - 1 such than n = / is presented by using a Steiner system. Some other efficient schemes are also presented.

This paper presents implicit representation of binary decision diagrams (implicit BDDs) as a new effecient data structure for Boolean functions. A well-known method of representing graphs by binary decision diagrams (BDDs) is applied to BDDs themselves. Namely, it is a BDD representation of BDDs. Regularity in the structure of BDDs representing certain Boolean functions contributes to significant reduction in size of the resulting implicit BDD repersentation. Since the implicit BDDs also provide canonical forms for Boolean functions, the equivalence of the two implicit BDD forms is decided in time proportional to the representation size. We also show an algorithm to maniqulate Boolean functions on this implicit data structure.

This letter presents a new design method for approximate inverse systems using all-pass networks. The efficacy of approximate inverse systems for input and parameter estimation of nonminimum phase systems is well recognized. in the previous methods, only time domain design of FIR (finite impulse response) type approximate inverse systems were considered. Here, we demonstrate that IIR (infinite impulse response) type approximate inverse systems outperform the previous methods. A nonlinear optimization technique is adopted for designing the proposed system in the frequency domain. Numerical examples are also presented to show the effectiveness of the proposed method.

A new methodology for simulation-based CMOS process design has been proposed, using a Hierarchical Response Surface Method (HRSM) and an efficient experimental calibration. The design methodology has been verified using a 0.4 micron CMOS process. The proposed HRSM achieved a 60% reduction of process and device design cost in comparison with those of conventional TCAD. The procedure was performed in conjunction with an experimental calibration technique to provide a reliable threshold voltage prediction including process variation effects. The total CPU cost was 200 hr. on SUN SPARC 10 and the error of the predicted threshold voltage was less than 0.02 V.

A design method of 2-D lattice digital filter using the Genetic Algorithm (GA) is proposed. By using the GA. 2-D all-pole lattice filter with the cascade connection of transversal (all-zoro) filter is designed directly from a given desired frequency responce.

We have developed a method to automatically generate a multi-input-adder circuit for an irregular array of partial products. "FASTOOL," an FIR Filter Automatic Synthesis TOOL for an HDL design environment, is proposed for use with this method and with conventional filter coefficient design programs. Filter design from specifications to the structure of Verilog-HDL has been automated. It is possible for a system designer to quickly perform filter LSI optimization by balancing cost and performance.

In this paper we describe a method for resynthesizing the controller of a design for a fixed datapath with the objective of increasing the design's throughput by minimizing its total execution time. This work has tremendous potential in two important areas: one, design reuse for retargetting datapaths to new libraries, new technologies and different bit-widths; and two, back-annotation of physical design information during High-Level Synthesis (HLS), and subsequent adjustment of the design's schedule to account for realistic physical design information with minimal changes to the datapath. We present our approach using various formulations, prove optimality of our algorithm and demonstrate the effectiveness of our technique on several HLS benchmarks. We have observed improvements of up to 34% in execution time after straightforward application of our controller resynthesis technique to the outputs of HLS.

We propose a distributed operation system platform for optical cable networks. This distributed platform is an extension of the previously proposed platform for a flexible cable network operation. The concept of the unit platform has been proposed for the distributed operation system platform. By using this concept, we discuss the system upgrade including the connection to other operation systems. We use an object-oriented software technology for designing the distributed operation system platform. The prototype system has been constructed using C++ programing language and the evaluated results are shown.

One of the major open issues in neural network research includes a Network Designing Problem (NDP): find a polynomial-time procedure that produces minimal structures (the minimum intermediate size, thresholds and synapse weights) of multilayer threshold feed-forward networks so that they can yield outputs consistent with given sample sets of input-output data. The NDP includes as a sub-problem a Network Training Problem (NTP) where the intermediate size is given. The NTP has been studied mainly by use of iterative algorithms of network training. This paper, making use of both rate distortion theory in information theory and linear algebra, solves the NDP mathematically rigorously. On the basis of this mathematical solution, it furthermore develops a mathematical solution Procedure to the NDP that computes the minimal structure straightforwardly from the sample set. The Procedure precisely attains the minimum intermediate size, although its computational time complexity can be of non-polynomial order at worst cases. The paper also refers to a polynomial-time shortcut to the Procedure for practical use that can reach an approximately minimum intermediate size with its error measurable. The shortcut, when the intermediate size is pre-specified, reduces to a promising alternative as well to current network training algorithms to the NTP.

High speed GaAs ICs (Integrated Circutis) using FETs (Field Effect Transistors) are reported. As the fabricating techniques, ion implantation processes for both 0.5 µm and 0.2 µm gate FETs using W/Al refractory metal and 0.2 µm recessed gate process with MBE grown epitaxial wafers are shown. These fabrication processes are selected depending on the circuit speed and the integration level. The outline of the circuit design and the examples of ICs, which are developed for 10 Gb/s optical communication systems, are also shown with the obtained characteristics.

This paper describes, from a system architectural viewpoint, how knowledge-based technologies have been utilized in developing EXLOG (an LSI circuit synthesis system) and SOFTEX (a software synthesis system) inside the authors' projects. Although the system architectures for EXLOG and SOFTEX started from the same production systems, consisting of transformation rules in the middle of the 1980's, both branched off in different directions in the 1990's. Based on experiences with EXLOG and SOFTEX, the differences between LSI and software design models are discussed, and the future directions are indicated for the knowledge-based design system architectures.

Time-frequency representations (TFRs) have been developed as tools for analysis of non-stationary signals. Signal dependent TFRs are known to perform well for a much wider range of signals than any fixed (signal independent) TFR. This paper describes customised and sequential versions of the signal dependent TFR proposed in [1]. The method, which is based on the use of the Radon transform at distance zero in the ambiguity domain, is simple and effective in dealing with both simulated and real data. The use of the described method for time-scale analysis is also presented. In addition, the paper investigates a simple technique for detection of noisy chirp signals using the Radon transfrom in the ambiguity domain.

This paper describes a novel input-free MOS VT extractor circuit. The circuit consists of a bias voltage block and a novel VT extractor block. The proposed VT extractor block has the advantages of the ground-referenced output, low influence of the nonideality, few numbers of transistors and no influence of the PMOS process. The PSpice simulations show the supply voltage range and the bias voltage range of the proposed circuit are wider than those of Johnson's or Wang's.