The most creative tasks in synthesizing pipelined data paths executing software descriptions are determinations of latency and stage of pipeline, operation scheduling and hardware allocation. They are interrelated closely and depend on each other; thus finding its optimal solution has been a hard problem so far. By using simulated annealing methodology, these three tasks can be formulated as a three dimensional placement problem of operations in stage, time step and functional units space. This paper presents an efficient method based on simulated annealing to provide excellent solutions to the problem of not only the determinations of latency and stage of pipeline, operation scheduling and hardware allocation simultaneously, but also the pipelined data path synthesis under the constraints of performance or hardware cost. It is able to find a near optimal latency and stage of pipeline, an operation schedule and a hardware allocation in a reasonable time, while effectively exploring the existing tradeoffs in the design space.

In this paper, we discuss design of quadrature mirror filter (QMF) banks using digital allpass networks in the frequency domain. In the QMF banks composed of a parallel connection of two allpass networks, both aliasing error and amplitude distortion are always completely canceled. Therefore, we only need to design the analysis filters and eliminate phase distortion of the overall transfer function. We consider design of the QMF banks in two cases where phase responses of the filters are repuired or not required. In the case where the phase responses are not required, the design problem can be reduced to design of phase difference of two allpass networks. In the case where the phase responses are required, we present a procedure for designing the QMF banks with both equiripple magnitude and phase responses.

A novel method is presented for designing discrete coeffcient FIR linear phase filters using Hopfield neural networks. The proposed method is based on the minimization of the energy function of Hopfield neural networks. In the proposed method, the optimal solution for each filter gain factor is first searched for, then the optimal filter gain factor is selected. Therefore, a good solution in the specified criterion can be obtained. The feature of the proposed method is that it can be used to design FIR linear phase filters with different criterions simultaneously. A design example is presented to demonstrate The effectiveness of the proposed method.

The investigation of device functions required from the systems point of view will be important for the development of the next generation of VLSI devices and systems. In this paper, a super pass transistor (SPT) model is presented as a quantum device candidate for future VLSI systems based on multiple-valued logic. A possible quantum device structure for the SPT model is also described, which employs the concepts of a lateral-resonant-tunneling quantum-dot transistor and a heterostructure field-effect transistor. Since it has the powerful capability of detecting multiple signal levels, the SPT will be useful for the implementation of highly compact multiple-valued VLSI systems. To exploit the functionality of the SPT, a super pass gate (SP-gate) corresponding to a single SPT is proposed as a multiple-valued universal logic module. The mathematical properties of the SP-gate are discussed. A design method for a multiple-valued SP-gate network is presented. An application of SP-gates to a multiple-valued image processing system is also demonstrated. The SP-gate network for the multiple-valued image processing system is evaluated in comparison with the corresponding NMOS implementation in terms of the number of transistors, interconnections and cascaded transistor stages. The size of a generalized series-parallel SP-gate network is also evaluated in comparison with a functionally equivalent multiple-valued series-parallel MOS pass transistor network. The results show that highly compact multiple-valued VLSI systems can be achieved if the SPT-model can be realized by an actual quantum device.

A bottleneck identification methodology is proposed for the performance-oriented design of shared-bus multiprocessors, which are composed of several major subsystems (e.g. off-chip cache, bus, memory, I/O). A subsystem with the longest access time per instruction is the one that limits processor performance and creates a bottleneck to the system. The methodology also facilitates further refined analysis on the access time of the bottleneck subsystem to help identify the causes of the bottleneck. Example performance model of a particular shared-bus multiprocessor architecture with separate address bus and data bus is developed to illustrate the key idea of the bottleneck identification methodology. Accessing conflicts in subsystems and DMA transfers are also considered in the model.

The goal of this paper is to propose a new symbolic model checking approach named time-space modal model checking, which could be applicable to verification of bit-slice microprocessor of infinite bit width and one dimensional systolic array of infinite length. A simple benchmark result shows the effectiveness of the proposed approach.

This paper presents the concept of k-FR circuits. The controllability of such a circuit is high due to its special structure. It is shown that all stuck-at faults and stuck-open faults in a k-FR circuit can be detected and located by k(k1)1 test vectors under the highly observable condition which assumes the output of every gate to be observable. k is usually two or three. This paper also presents an algorithm for converting an arbitrary combinational circuit into a k-FR circuit. A k-FR circuit is easy to test when using technologies such as the electron-beam probing, the current measurement, or the CrossCheck testability solution.

In the final stages of VLSI testing, improved quality VLSI testing is an important subject for ensuring reliability in the forwarded VLSI market. On the other hand, developments in high integration technology have resulted in an increased number of functional blocks in VLSI devices and an increased number of gates for each terminal. Consequently, it has become more difficult to improve the quality of VLSI tests. We have developed a new test method in addition to conventional testing methods intended for improving the test coverage in VLSI tests. This new test method analyzes the relationship between IDDq (Quiescent Power Supply Current) of DUT and DUT failure by applying the concept of the toggle rate. Accordingly, in this paper we report that the results of IDDq testing confirm a correlation with defect level.

Currently there is considerable world-wide speculation regarding the introduction of optical fiber cable into access networks, because optical fiber has a big potential for providing attractive multimedia services. Since optical fiber cable can provide a variety of grade of services, high-reliability of cable networks would be required compared with the conventional copper cable networks. To develop multimedia telecommunication networks as an infrastructure, it is urgent to clarify the highly reliable optical fiber cable network architecture. Since cable network architecture deeply depends on regional conditions such as demand, area size, duct layer networks (consisting of ducts, manholes, tunnels, feeder points etc.), it is necessary to develop a cable network designing tool with user-friendly interfaces for efficiently evaluating cable network architectures. This paper firstly proposes the heuristic algorithms enhanced by the disjoint-shortest-path and the depth-first-search methods that would be applicable for real access networks. Secondly, the design method of highly reliable optical fiber cable network based on the heuristic algorithms in terms of network cost and unavailability caused by cable breakdown is proposed. It can design the combination of star- and loop-shaped (where two diversified routes exist between a feeder point and central office) cable network. Furthermore, comparison with the conventional design method which simply applies star- or loop-shaped cable network is done in terms of economy and reliability on real access networks in the Tokyo metropolitan area. It is concluded that the proposed method can reduce the network cost further and realize a short unavailability value compared with the conventional method.

Current testing has been proposed as an alternative technique for testing fully CMOS digital LSIs. Current testing has higher fault coverage than conventional stuck-at fault (SAF) testing and is more economical because it detects a wide range of faults and requires fewer test vectors than does SAF testing. We have proposed a current testing that measures the integral of the power supply current (IDD) during one clock period including the switching current. Since this method cannot be affected by the switching current, it can be used to test an LSI operating at a relatively high clock freuqnecy. This paper presents an improved current testing method for CMOS digital and analog LSIs. The method uses two current values (i.e., an upper limit and a lower limit) and judges the circuit under test to be faulty if the measured IDD is outside these limits. The proposed current testing is evaluated here for some kinds of faults (e.g., the bridging fault and the breaking fault) in digital and mixed-signal LSIs, and its efficiency of the current testing using SPICE3.

An optimum design scheme for logical network topologies on a Flexible Multi-QoS Logical ATM Network, named Full-Net, is proposed. Full-Net offers high-quality Virtual-Path (VP) networks and controls end-to-end QoS only at the VP-network's access points. To develop the optimum network topology for multimedia traffic in a single ATM network, a logically con figured Virtual Channel Handler (VCH) interconnection network is associated with each QoS class. Many logical networks can be mapped at the same time on the same network, because mapping is independent of the network's physical implementation. To achieve an optimum design scheme for logical networks, the number of disjoint routes is introduced as the parameter used to optimize logical network topology. The number of disjoint routes is chosen so as to maximize total network efficiency. The optimum number of disjoint routes depends on the required QoS, VC-traffic characteristics, and traffic demand. By choosing the relevant cost characteristics, the network operator can easily maximize network efficiency and provide customers with the QoS they request at minimum cost. The proposed optimum multi-QoS network design scheme on a Full-Net architecture is an efficient solution to implementing multi-QoS control in an ATM network.

This paper describes an innovative heat-pipe cooling technology for asynchronous transfer mode (ATM) switching multichip modules (MCMs) operating with a throughput of 40 Gb/s. Although high-speed ATM link-wires are connected at the top surface of the MCMs, there is no room to cool the MCM by forced air convection, because power and the system clock signal are supplied by connectors on the rear and periphery of the MCM. We therefore chose to attach a cold-plate to the back of each MCM. The condenser part of the heat pipe, which is mounted behind the power supply printed circuit board, is cooled by low-velocity forced air. Total power dissipation is about 30 watts per MCM. With a 2 m/s foreced airflow, the sub-switching-element module (four MCMs) operates at a throughput of 80 Gb/s with a maximum junction temperature of less than 85. Measured thermal resistance between the switch LSI junction and air is about 6/W. This heat-pipe cooling system has a small system footprint, compact hardware, and good cooling capacity.

A new approximation calculation method, named the Recursive Matrix-calculation (RM) method, is proposed. It uses matrix calculation to determine the number of link disjoint paths under a hop link number constraint, i.e. hop limit. The RM method does not overestimate the number of link disjoint paths. When networks are designed by this method, network reliability is perfectly guaranteed. Moreover, the RM method is based on matrix calculation, so CPU time can be reduced by using super-computers equipped with vector processors. Simulation results confirm that the RM method yields rapid approximations that are conservative. Thus the proposed method is very useful for designing reliable multimedia networks.

When communication network planning-design is performed, especially in a short-term case, it is important to utilize existing facilities in the construction of the new network. In this paper, link capacity assignment problem (CA problem) for packet-switched networks is investigated with the consideration of the existing network. To deal with this, per-unit cost of existing link capacity is thought to be less than that of newly installed capacity and a link cost function is modeled by a non-linear, non-differentiable one which is composed of two portions of capacity cost. After formulating the CA problem, two optimum algorithms derived from Lagrange multiplier method are presented and a modified algorithm is used for solving the CA problem in order to reduce the computation time. Some numerical results show that according to the values of link traffic flows, there will be links whose capacities must be set equally to the existing values. Moreover, when link cost difference is introduced in the CA problem, the number of links that the capacities of which have to be changed from existing values is less than that of linear cost function case, i.e., the case without consideration of the cost difference in link capacity.

We describe a formal verification algorithm for pipelined processors. This algorithm proves the equivalence between a processor's design and its specifications by using rewriting of recursive functions and a new type of mathematical induction: extended recursive induction. After the user indicates only selectors in the design, this algorithm can automatically prove processors having more than 10(1010) states. The algorithm is manuary applied to benchmark processors with pipelined control, and we discuss how data width, memory size, and the numbers of pipeline stages and instructions influence the computation cost of proving the correctness of the processors. Further, this algorithm can be used to generate a pipeline invariant.

Optical path technology that employs both WDM/FDM and wavelength routing will play a key role in supporting future high bandwidth transport networks. WP/VWP (Wavelength Path/Virtual Wavelength Path) technologies are very effective in realizing optical path networks. In these networks, since photonic wavelengths are scarce resources, the number of wavelengths required to construct the network must be minimized. However, the wavelength assignment problem, minimizing the number of wavelengths, is an NP-complete problem. Solving this problem heuristically is an important issue for designing large-scale WP/VWP based networks that are also practical. To realize optical path networks, we need to develop path accommodation design algorithms that heuristically solve the wavelength assignment problem. This paper proposes novel path accommodation design algorithms for WP/VWP networks that minimize the number of wavelengths required. We numerically elucidate that the numbers of wavelengths required for active WPs and VWPs are almost equal. When link failure restoration is considered, they are different; more wavelengths are needed with the WP scheme than with the VWP scheme. It is also demonstrated that the proposed algorithms are applicable to a large scale network design.

We give a tutorial on high-level synthesis of VLSI. The evolution of digital system synthesis techniques and the need for higher level design automation tools are first discussed. We then point out essential issues to the successful development and acceptance by the designers of a high-level synthesis system. Techniques that have been proposed for various subtasks of high-level synthesis are surveyed. Possible applications of the high level synthesis in area other than chip design are forecast. Finally, we point out several directions for possible future research.

A key element in the CDMA transmission is DS spreading. Spreading in a DS/SSMA system are provided in two categories-synchronization and data. For synchronization sequences, good auto-correlation and cross-correlation properties are required in order to guarantee fast acquistion with a minimum false alarm probability. On the other hand, the auto-correlation property may not be so important in data spreading since synchronization is obtained by synchronization spreading. In this paper we provide a set of synchronization sequences and a set of data sequences--each a set of binary N-tuples--that have the necessary correlation constraints.

In improving channel utilization in microcellular systems, adaptive channel allocation using distributed control has been reported to be effective. We describe an analytical approximation algorithm for channel dimensioning of distributed adaptive channel allocation. We compare our analytical results with simulation results and show the characteristics of permissible load as a function of the number of base station channels based on our method. Finally we illustrate traffic design and administration based on our algorithm.

In this paper we propose a co-design method for control systems using combination of models. By co-design," we mean a cooperative design method in which the behavior of the entire system is simulated as a single model while parameters of the system are being optimized. Our co-design method enables the various subsystems in the system, which have been designed independently as tasks assigned to different designers in the traditional design method, to be designed simultaneously in a unified cooperative way from the system-wide perspective of a system designer. Our proposed method combines models of controlling and controlled subsystems into a single model for the behavior of the entire control system. After the optimum control conditions are determined through simulation of the combined models, based on the corresponding algorithms and parameters, ASIC design proceeds quickly with accurate verification using iterative replacements of the behavior model by the electronic circuit model. To evaluate the proposed method, we implemented a design environment. We then applied our method to the design of ASICs in three test cases (in a control system and in audio-visual systems) to investigate its effectiveness. This paper introduces the concepts of the proposed co-design method, the design environment and the experimental results, and points out the new issues for system design.