This paper describes the design principles, the specification, and evaluations of a new 128-bit block cipher E2, which was proposed to the AES (Advanced Encryption Standard) candidates. This algorithm supports 128-bit, 192-bit, and 256-bit secret keys. The design philosophy of E2 is highly conservative; the structure uses 12-round Feistel as its main function whose round function is constructed with 2-round SPN structure, and initial/final transformational functions. E2 has practical security against differential attack, linear attack, cryptanalysis with impossible differential, truncated differential attack, and so on. Furthermore, E2 can be implemented efficiently and flexibly on various platforms because the primitive operations involve byte length processing.

This paper reports the design and characteristics of an aerial optical drop cable incorporating electric power wires, which was developed for a new π-system. The new system is called the power supply HUB π-system, in which commercial AC electric power is received at a central location of several optical network units (ONUs), and is distributed to each ONU by the aerial optical/electric drop cable. We describe the requirements for the cable, which guarantee a 20-year lifetime. We designed the cross-sectional structure of the cable, based on system requirements and operation requirements, and determined the strength wire type and diameter, based on the optical fiber failure prediction theory and a cable strain requirement. We confirmed that the cables, manufactured as a trial, have stable characteristics, which satisfy the above requirements. The optical/electric drop cables will be introduced in autumn 1999.

I would like to draw the attention of the editorial board of IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences and its readers to a recent paper, Tianruo Yang, "The integrated scheduling and allocation of high-level test synthesis," vol. E82-A, no. 1, January 1999, pp. 145-158. (Here we call this paper the Yang's paper. ) Yang did not give the correct information about the originality of the paper. I will point out that the writings (and the idea accordingly) of section 6 of Yang's paper came from papers [1] and [2].

This paper discusses factorization of bent function type complex Hadamard matrices of order pn with a prime p. It is shown that any bent function type complex Hadamard matrix has symmetrical factorization, which can be expressed by the product of n matrices of order pn with pn+1 non-zero elements, a matrix of order pn with pn non-zero ones, and the n matrices, at most. As its application, a correlator for M-ary spread spectrum communications is successfully given, which can be simply constructed by the same circuits with reduced multiplicators, before and behind.

This paper presents a quadriphase sequence pair, whose aperiodic auto-correlation functions for non-zero shifts and cross-one for any shift take pure imaginary values. Functions for pairs of length 2n are formulated, which map the vector space of order n over GF(2) to Z4. It is shown that they are bent for any n, such that their Fourier transforms take all the unit magnitude.

As many research works are based on some previous results, my paper, namely The Integrated Scheduling and Allocation of High-Level Test Synthesis, makes use of some techniques by T. Kim. However, I did not state explicitly that some parts of my work are based on Kim's approach although I have referred to his paper. I would like to express my deep apology to Kim for not having emphasized Kim's contribution to my work. But my intention was not to steal Kim's ideas. I would like to emphasize the following difference.

This paper proposes an ASIP performance optimization method taking clock frequency into account. The performance of an instruction set processor can be measured using the execution time of an application program, which can be determined by the clock cycles to perform the application program divided by the applied clock frequency. Therefore, the clock frequency should also be tuned in order to maximize the performance of the processor under the given design constraints. Experimental results show that the proposed method determines an optimal combination of FUs considering clock frequency.

This paper describes a novel layout optimization technique using electromagnetic (EM) simulation. Simple equivalent circuits fitted to EM simulation results are employed in this method, to present a modification guide for a layout pattern. Fitting errors are also investigated with some layout patterns in order to clarify the applicable range of the method, because the errors restrict the range. The method has been successfully adopted to an X-band low noise MMIC amplifier (LNA). The layout pattern of the amplifier was optimized in only two days and the amplifier has achieved target performances--a 35 dB gain and a 1.7 dB noise figure--in one development cycle. The effective chip area has been miniaturized to 4.8 mm2. The area could be smaller than 70% in comparison with a conventional layout MMIC.

In the hardware synthesis methods with high level languages such as C language, optimization quality of the compilers has a great influence on the area and speed of the synthesized circuits. Among hardware-oriented optimization methods required in such compilers, minimization of the bit length of the data-paths is one of the most important issues. In this paper, we propose an estimation algorithm of the necessary bit length of variables for this aim. The algorithm analyzes the control/data-flow graph translated from C programs and decides the bit length of each variable. On several experiments, the bit length of variables can be reduced by half with respect to the declared length. This method is effective not only for reducing the circuit area but also for reducing the delay of the operation units such as adders.

This paper presents an algorithm for the scan-chain optimization problem in multiple-scan design methodology. The proposed algorithm, which consists of four phases, first determines pairs of scan-in and scan-out pins (Phase 1), and then assigns flip-flops to scan-paths by using a graph theoretical method (Phase 2). Next the algorithm decides connection-order of flip-flops in each scan-path by using TSP (Traveling Salesman Problem) heuristics (Phase 3), and finally exchanges flip-flops among scan-paths in order to reduce total scan-path length (Phase 4). Experiments using actual design data show that, for ten scan-paths, our algorithm achieved a 90% reduction in scan-test time at the expense of a 7% total scan-path length increase as compared with the length of a single optimized scan-path. Also, our algorithm produced less total scan-path length than other three possible algorithms in a reasonable computing time.

In this paper, a novel application specific power optimization technique utilizing small instruction ROM which is placed between an instruction cache or a main program memory and CPU core is proposed. Our optimization technique targets embedded systems which assume the following: (i) instruction memories are organized by two on-chip memories, a main program memory and a subprogram memory, (ii) these two memories can be independently powered-up or powered-down by a special instruction of a core processor, and (iii) a compiler optimizes an allocation of object code into these two memories so as to minimize average of read energy consumption. In many application programs, only a few basic blocks are frequently executed. Therefore, allocating these frequently executed basic blocks into low power subprogram memory leads significant energy reduction. Our experiments with actual ROM (Read Only Memory) modules created with 0.5 µm CMOS process technology, and MPEG2 codec program demonstrate significant energy reductions up to more than 50% at best case over the previous approach that applies only divided bit and word lines structure.

The subliminal channel is one of the methods for hiding a message in other messages. Simmons has shown conjectures on the upper bound to the bandwidth of a subliminal channel. This paper proposes a new broad-band subliminal channel embedded in the ESIGN. The bandwidth of the proposed subliminal channel is wider than that of the previous one, and it exceeds the upper bound that Simmons has conjectured. Namely, we disprove the conjectures due to Simmons. We also show that it is possible to construct the subliminal channel even if the transmitter and the subliminal receiver do not have any key in common.

In pattern recognition using neural networks, it is very difficult for researchers or users to design optimal neural network architecture for a specific task. It is possible for any kinds of neural network architectures to obtain a certain measure of recognition ratio. It is, however, difficult to get an optimal neural network architecture for a specific task analytically in the recognition ratio and effectiveness of training. In this paper, an evolutional method of training and designing feedforward neural networks is proposed. In the proposed method, a neural network is defined as one individual and neural networks whose architectures are same as one species. These networks are evaluated by normalized M. S. E. (Mean Square Error) which presents a performance of a network for training patterns. Then, their architectures evolve according to an evolution rule proposed here. Architectures of neural networks, in other words, species, are evaluated by another measurement of criteria compared with the criteria of individuals. The criteria assess the most superior individual in the species and the speed of evolution of the species. The species are increased or decreased in population size according to the criteria. The evolution rule generates a little bit different architectures of neural network from superior species. The proposed method, therefore, can generate variety of architectures of neural networks. The designing and training neural networks which performs simple 3 3 and 4 4 pixels which include vertical, horizontal and oblique lines classifications and Handwritten KATAKANA recognitions are presented. The efficiency of proposed method is also discussed.

In this paper, we study the link capacity assignment problem in packet-switched networks (CA problem) focusing on the case where link cost function is a piecewise linear concave function. This type of cost function arises in many communication network design problems such as those arising from developments in communication transmission technologies. It is already known that the method of link set assignment is applicable for solving the CA problem with piecewise linear convex cost function. That is, each link in the network is assigned to one of a group of specific sets, and checked for link set contradiction. By extending the method of link set assignment to the case of piecewise linear concave cost function, an important characteristic of the optimal solution of the CA problem is derived. Based on this characteristic, the non-differentiable link cost function can be treated as a differentiable function, and a heuristic algorithm derived from the Lagrange multiplier method is then proposed. Although it is difficult to determine the global optimum of the CA problem due to its non-convexity, it is shown by numerical results that the solution obtained from the proposed algorithm is very close to the global optimum. Moreover, the computation time is linearly dependent on the number of links in the problem. These performances show that the proposed algorithm is very efficient in solving the CA problem, even in the case of large-scale networks.

This paper presents a novel method of an on-sensor motion vector estimation. One of the key techniques is an iterative block matching algorithm using high-speed interpolated pictures. This technique allows us to estimate the video-rate (30 frame/s) motion vectors accurately from the motion vectors obtained at high-speed frames. The proposed iterative block matching reduces the computational complexity by a factor of more than one tenth compared to the conventional full search block matching algorithm. This property is particularly useful for the reduction of the power dissipation of video encoder. Another proposed technique is a high-speed non-destructive image sensing. This technique is essential to obtain high-speed interpolated pictures while maintaining high image quality in video-rate image sensing. The estimated power dissipation of the designed CMOS image sensor is sufficiently low, allowing us to achieve a totally low-power design of one-chip CMOS cameras integrating an image sensor and a video encoder.

In this paper, we present the theoretical development to stabilize a class of uncertain time-delay system. The system under consideration is described in state space model containing distributed delay, uncertain parameters and disturbance. The main idea is to transform the system state into an equivalent one, which is easier to analyze its behavior and stability. Then, a computational method of robust controller design is presented in two parts. The first part is based on solving a Riccati equation arising in the optimal control theory. In the second part, the finite dimensional Lyapunov min-max approach is employed to cope with the uncertainties. Finally, we show how the resulting control law ensures asymptotic stability of the overall system.

This paper treats the systematic design of chaos generators which are capable of generating continuous-time signals with prescribed probability density function and power density spectra. For a specific signal model a statistical analysis is performed such that the inverse problem, i. e. the calculation of the model parameters from prescribed signal characteristics, can be solved. Finally from the obtained model parameters and the model structure the signal generating system is constructed. The approach is illustrated by several examples.

This letter proposes an integrated approach to multimedia ATM network design. An optimization model that combines the physical layer design with the logical layer design is developed. A key feature of the model is that the objective to be maximized is a profit function. It includes more comprehensive cost functions for the physical and logical layers. A simple heuristic algorithm to solve the model is presented. It should be useful in practice for network designers and operators. Some numerical examples are given to illustrate the application of the model and the algorithm.

This paper describes the benefit of utilizing the unary function generators in a multiple-valued Programmable Logic Array (PLA). We will clarify the most suitable PLA structure in terms of the array size. The multiple-valued PLA considered here has a structure with two types of function generators (literal and unary function generators), a first-level array and a second-level array. On investigating the effectiveness to reduce the array size, we can pick up four form PLAs: MAX-of-TPRODUCT form, MIN-of-TSUM form, TSUM-of-TPRODUCT form and TPRODUCT-of-TSUM form PLAs among possible eight form PLAs constructing from the MAX, MIN, TSUM and TPRODUCT operators. The upper bound of the array sizes with v UGs is derived as (log2ppv + p(n-v) + 1) pn-1 to realize any n-variable p-valued function. Next, experiments to derive the smallest array sizes are done for 10000 randomly generated functions and 21 arithmetic functions. These results conclude that MAX-of-TPRODUCT form PLA is the most useful in reducing the array size among the four form PLAs.

This paper presents a low-power video A/D conversion technique using features of moving pictures. Neighboring frames in typical video sequences and neighboring pixels in each video frame are highly correlated. This property is effectively used for the video A/D conversion to reduce the number of comparators and the resulting power consumption. A set of reference voltages is given to a comparator array so that the iterative A/D conversion converges in the logarithmic order of the prediction error. Simulation results using standard moving pictures showed that the average number of iterations for the A/D conversion is less than 3 for all the moving pictures tested. In the proposed 12 b A/D converter, the number of comparators can be reduced to about 1/5 compared with that of the two-step flash A/D converters, which are commonly used for video applications. The A/D converter is particularly useful for the integration to CMOS image sensors.