CTL (Computation Tree Logic) model checking is a formal method for design verification that checks whether the behavior of the verified system is contained in that of the requirements specification. If this check doesn't pass, the CTL model checker generates a subset of fair states which belongs to the system but not to the specification. In this letter, we present an incremental method which successively modifies the latest verification result each time the design is modified. Our incremental algorithm allows the designer to make changes in terms of addition or subtraction of fair CTL formulas, or fairness constraints on acceptable behavior from the problem statement. Then, these changes are adopted to update the set of fair states computed earlier. Our incremental algorithm is shown to be better than the current non-incremental techniques for CTL model checking. Furthermore, a conclusion supported by the experimental results is presented herein.

In this paper, a novel design method for bandpass filter with attenuation poles (BAP) is presented. The changed inverter element values due to inserting either capacitors or inductors can be optimized using the linear relationship between inverter element values of a conventional bandpass filter (BPF) and those of the BAP using the Touchstone program. A 1800-1825 MHz bandpass filter with attenuation poles for duplexers is designed and fabricated using coaxial dielectric resonators. The validity of this design approach is demonstrated by a computer simulation. The resonators are simulated equivalently as shorted lossy transmission lines. The measured results of center frequency, bandwidth, and attenuation pole frequencies closely agree with the design values.

An intrinsic property of a tapped resonator is elucidated here, and a novel bandpass filter (BPF) with improved skirt characteristics based on a tapped half-wavelength resonator is proposed by this intrinsic property. "Tapping" for both I/O and interstage couplings of the resonator is the key concept here because a resulting open-ended resonator makes shunt open stubs which give anti-resonance near the center frequency. Multiple attenuation poles appear near the center frequency, namely, close to the passband. A BPF is designed on the basis of the general filter theory with a narrow band approximation. An experiment is carried out to confirm the concept by using a coplanar structure. The expected bandpass characteristics with multiple attenuation poles have been obtained by the novel BPF designed by the present concept.

When designing microwave amplifiers, it is the task to select values of the source (input generator) and load reflection coefficients for the transistor, to achieve certain amplifier performance requirements and ensure stability. For unconditionally stable transistors, simultaneous conjugate matching can be achieved using well-known design formulae. Under this condition, the gain is maximised, and the input and output ports are matched. On the other hand when the transistor is conditionally stable, source and load reflection coefficients are selected using graphical design methods, involving gain and stability circles. To eliminate the reliance on graphical techniques, this paper shows the derivation of explicit design formulae that ensure maximum gain for a minimum specified safety margin, with one port matched. In this work, the safety margin is the distance between the chosen source or load reflection coefficient and its respective stability circle. In a production environment, where the circuit and transistor parameters are subject to random variations, the safety margin therefore makes allowance for such variations. This paper shows that the design problem for conditionally stable transistors can be reduced from the selection of values for two complex variables (port terminations) to the selection of the value for just one scalar variable.

Design concepts and backgrounds of a 3-dimensional semiconductor process simulator are presented. It is designed to become a basis of developing semiconductor process models. An input language is designed to realize flexibly controlling simulation sequence, and its interpreter program is designed to accept external software to be controlled and to be integrated into a system. To realize data-exchanges between the process simulator and other software, a self-describing data-file format is designed and related program libraries are developed. A C++ class for solving drift-diffusion type partial-differential-equation in a three-dimensional space is developed.

A new design hierarchy in TCAD is discussed with emphasis on a design of IC interconnects and gate patterns. Two design methodologies for gate patterns at a CMOS cell level and multilevel interconnect scheme at a chip level are proposed. This approach generates the layout design rules of gate patterns, considering the fabrication process and pattern layout dependency, and allows a design of multilevel interconnect scheme at the initial phase of technology development.

In practical logic design circuits are built by composing certain types of gates. Each gate itself is a simple circuits with one, two or three inputs and one output, which implements an elementary logic function. These functions are called the generators. For the general purpose the set of generators is considered to be functionally complete, i. e. , it is able to express any logic function under chosen rules compositions. A basis is a functionally complete set of logic functions that contains no complete proper subset. Providing compactness and expressibility of the generators the notion of a basis, however, ignores the optimality of implementations. Efficiently irreducible generating set, termed ε-basis, is an irreducible set of generators which guarantees an optimal implementation of every function, with respect to the number of literals in its formal expression. The notion of ε-basis is significant in the composition of functions, since the classical definition of basis does not consider the efficiency of implementation. In case of Boolean functions, for two-input (dyadic) generators it has been shown that an ε-basis consists of all monadic functions, constants, and only two dyadic functions from certain classes. In this paper, expanding the domain of basic operations from dyadic to triadic, we study the efficiency of sets of 3-input gates as generators. This expansion decreases the complexity of functions (hence, the complexity of functional circuits to be designed). Gaining an evident merit in the complexity, we have to pay a price by a considerable increase of the number of such generators for the multiple valued circuits. However, in the case of Boolean operations this number is still very small, and it will certainly be useful to consider this approach in the practical circuit design. This paper provides a criterion for a generating set of triadic operations of k-valued logic to be efficiently irreducible. In the case of Boolean functions it is shown that there exist exactly five types of classes of triadic operations which constitute an ε-basis. A typical example of generator set which forms a triadic ε-basis, is also shown.

This paper presents a new approach to designing arithmetic circuits by using a graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG). The key idea of the proposed method is to introduce a higher level of abstraction for arithmetic algorithms, in which arithmetic circuit structures are modeled as data-flow graphs associated with specific number representation systems. The EGG system employs evolutionary operations to transform the structure of graphs directly, which makes it possible to generate the desired circuit structure efficiently. The potential capability of EGG is demonstrated through an experiment of generating constant-coefficient multipliers.

In highly reliable communication network design, disjoint paths between pairs of nodes are often needed in the design phase. The problem of finding k paths which are as diverse as possible and have the lowest total cost is called a k-best paths problem. We propose an algorithm for finding the k-best paths connecting a pair of nodes in a graph G. Graph extension is used to transfer the k-best paths problem to a problem which deploits well-known maximum flow (MaxFlow) and minimum cost network flow (MCNF) algorithms. We prove the k-best paths solution of our algorithm to be an optimal one and the time complexity is the same as MCNF algorithm. Our computational experiences show that the proposed algorithm can solve k-best paths problem for a large network within reasonable computation time.

This paper presents a heuristic algorithm that minimizes the delay of the given circuit through a two-pass cell selection in cell-based design. First, we introduce a new graph, called candidate web, which conveniently represents all cell combinations available for the implementation of the given circuit. We, then, present an efficient method to obtain a tentative set of optimal cells, while estimating the delay of the longest path between each cell and the primary output on the candidate web. In this step, multiple cells are allowed to bind the same logic gate. Finally, we describe how the proposed approach actually selects the optimal cells from the tentative set, which would minimize the circuit delay. Experimental results on a set of benchmarks show that the proposed approach is effective and efficient in minimizing the delay of the given circuit.

In this paper, we present an efficient approach for technology scaling of MOS analog circuits by using circuit optimization techniques. Our new method is based on matching equivalent circuit parameters between a previously designed circuit and the circuit undergoing redesign. This method has been applied to a MOS operational amplifier. We were able to produce a redesigned circuit with almost the same performance in under 4 hours, making this method 5 times more efficient than conventional methods

This paper presents a new scheme of a low-power area-efficient pipelined A/D converter using a single-ended amplifier. The proposed multiply-by-two single-ended amplifier using switched capacitor circuits has smaller DC bias current compared to the conventional fully-differential scheme, and has a small capacitor mismatch sensitivity, allowing us to use a smaller capacitance. The simple high-gain dynamic-biased regulated cascode amplifier also has an excellent switching response. These properties lead to the low-power area-efficient design of high-speed A/D converters. The estimated power dissipation of the 10-b pipelined A/D converter is less than 12 mW at 20 MSample/s.

In this paper, we propose a method, called PORT-D, for optimizing CMOS logic circuits to reduce the average power dissipation. PORT-D is an extensional method of PORT. While PORT reduces the average power dissipation under the zero delay model, PORT-D reduces the average power dissipation by taking into account of the gate delay. In PORT-D, the average power dissipation is estimated by the revised BDD traversal method. The revised BDD traversal method calculates switching activity of gate output by constructing OBDD's without representing switching condition of a gate output. PORT-D modifies the circuit in order to reduce the average power dissipation, where transformations which reduce the average power dissipation are found by using permissible functions. Experimental results for benchmark circuits show PORT-D reduces the average power dissipation more than the number of transistors. Furthermore, we modify PORT-D to have high power reduction capability. In the revised method, named PORT-MIX, a mixture strategy of PORT and PORT-D is implemented. Experimental results show PORT-MIX has higher power reduction capability and higher area optimization capability than PORT-D.

This paper presents a high-level test synthesis algorithm for operation scheduling and data path allocation. Data path allocation is achieved by a controllability and observability balance allocation technique which is based on testability analysis at register-transfer level. Scheduling, on other hand, is carried out by rescheduling transformations which change the default scheduling to improve testability. Contrary to other works in which the scheduling and allocation tasks are performed independently, our approach integrates scheduling and allocation by performing them simultaneously so that the effects of scheduling and allocation on testability are exploited more effectively. Additionally, since sequential loops are widely recognized to make a design hard-to-test, a complete (functional and topological) loop analysis is performed at register-transfer level in order to avoid loop creation during the integrated test synthesis process. With a variety of synthesis benchmarks, experimental results show clearly the advantages of the proposed algorithm.

This letter examines outline measures of strength against the differential and linear cryptanalysis. These measures are useful to estimate the number of rounds giving an immune iterated cipher. This letter reports that the outline measures of strength are useful to relatively estimate the strength of generalized feistel ciphers.

This paper reports on an Intelligent CASE tool, applicable in a structured programming phase, or from detailed design to coding. This is automation of the bottom level in the hierarchical design process of detailed design and coding, where the largest man-hours are consumed. The main idea is that human designers use a CASE tool for the initial design of a software system, and the design knowledge is automatically acquired from the structured charts and stored in the knowledge base. The acquired design knowledge may be reused in designs. By reusing it, a similar software system may be designed automatically. It has been shown that knowledge acquired in this way has a Logarithmic Learning Effect. Based on this, a quantitative evaluation of productivity is made. By accumulating design experiences (e. g. 10 times), more than 80% of the detailing designs are performed automatically, and productivity increases by up to 4 times. This tool features universality, an essentially zero start-up cost for automatic design, and a substantial increase in software productivity after enough experiences have been accumulated. This paper proposes a new basic idea and its implementation, a quantitative evaluation applying techniques from Industrial Engineering, which proves the effectiveness of the proposed system.

This paper presents a new routing method that takes into account neighboring-wire-capacitance (inter-layer and intra-layer) constraints. Intermediate routing (IR) assigns each H/V wire segment to the detailed routing (DR) grid using global routing (GR) results, considering the neighboring-wire constraints (NWC) for critical nets. In DR, the results of IR for constrained nets and their neighboring wires are preserved, and violations that occur in IR are corrected. A simple method for setting NWC that satisfy the initial wire capacitance given in a set-wire-load (SWL) file is also presented. The routing method enables more accurate delay evaluation by considering inter-wire capacitance before DR, and avoids long and costly turnaround in deepsubmicron layout design. Experimental results using MCNC benchmark test data shows that the errors between the maximum delay from IR and that from DR for each net were less than 5% for long (long delay) nets.

For the improvement of software quality and productivity, the author aims at realizing a software development environment to develop software through utilizing the merits of group work. Since networking is necessary for collaborative software development, he has developed a software distributed development environment for collaborative software development. In this environment, discussions about software design are held through a communication network, and the contents of discussions are recorded as software design decisions and decision rationale. One feature of this environment is that the contents of discussions can be recorded in on-line real time and reused without reconstructing the information recorded through this environment. This paper clarifies the essential conditions for actualizing this environment and proposes an information structure model for recording the contents of discussions that actualizes the above-mentioned feature. The effectiveness of the proposed model is proved through an example of its application to software design discussions.

This paper proposes a new flexible hardware model for pipelined design optimization. Using together with an RTL floorplanner, the flexible hardware model makes accurate and fine design space exploration possible. It is quite effective for deep submicron technology since estimation at high level has become a difficult problem and the design tuning at lower level of abstraction makes up the full design optimization task. The experimental results show that our approach reduces the slack time in the pipeline stages then achieves higher performance with a smaller area.

The productivity of developing software for switching systems and the effects of using advanced software development methods were evaluated and analyzed. Productivity was found to be improved by using automatic code generation, simulator debugging, a hierarchical object-oriented software structure, and software-development-support tools. The evaluation showed that the total productivity was improved by about 20%, compared with a case where these efforts were not introduced. It also showed each effect of these methods and tools by evaluating their manpower saving ratios. These results are expected to benefit the development of various types of communication-switching and multimedia service systems. Also, our development-support tools and methods are expected to be the basis for attaining higher software development productivity.