This paper presents an application-specific, heterogeneous multiprocessor synthesis system, named HeMPS, that combines a form of Evolutionary Computation known as Differential Evolution with a scheduling heuristic to search the design space efficiently. We demonstrate the effectiveness of our technique by comparing it to similar existing systems. The proposed strategy is shown to be faster than recent systems on large problems while providing equivalent or improved final solutions.

An automated analog circuit synthesis based on reuse of topological features of 'prototype circuits' is proposed. The prototype circuits are designed by humans and suggested to the synthesis system as hints of configurations of new analog circuits to be synthesized by the system. The connections of elements in analog circuits are not generally systematic, but they would have some similarities to a circuit which has similar behaviors or functionalities. In the proposed process, the information on circuit connections is stored as sub-circuits extracted from the prototype circuits. And then, genetic algorithm is used to search for an optimum combination of the sub-circuits that achieves the desired electronic specifications. The combinations of sub-circuits are performed with a novel technique where the terminals of the sub-circuits are shared. The capabilities of the proposed method are demonstrated through an example of the synthesis.

A system level approach for a memory power reduction is proposed in this paper. The basic idea is allocating frequently executed object codes into a small subprogram memory and optimizing supply voltage and threshold voltage of the subprogram memory. Since large scale memory contains a lot of direct paths from power supply to ground, power dissipation caused by subthreshold leakage current is more serious than dynamic power dissipation. Our approach optimizes the size of subprogram memory, supply voltage, and threshold voltage so as to minimize memory power dissipation including static power dissipation caused by leakage current. A heuristic algorithm which determines code allocation, supply voltage, and threshold voltage simultaneously so as to minimize power dissipation of memories is proposed as well. Our experiments with some benchmark programs demonstrate significant energy reductions up to 80% over a program memory which does not employ our approach.

In this paper, we present an RTL design-space exploration method for high-level applications. We formulate the RTL design-space exploration into a performance-driven module selection problem. We devise a dynamic-programming algorithm to solve the problem. We present an exploration flow by integrating commercial synthesis and layout tools with our proposed method. Experimental results have demonstrated that generating AT-curve for all modules is the most time consuming task in the design-space exploration process. Using the proposed 3-point AT projection approach, our method can achieve on an average of 80% speed-up in run time and 90% accuracy in design estimation.

We propose a transistor sizing method that downsizes MOSFETs inside a cell to eliminate redundancy of cell-based circuits as much as possible. Our method reduces power dissipation of detail-routed circuits while preserving interconnects. The effectiveness of our method is experimentally evaluated using 3 circuits. The power dissipation is reduced by 75% maximum and 60% on average without delay increase. Compared with discrete cell sizing, the proposed method reduces power dissipation furthermore by 30% on average.

In this paper, a design of Programmable Logic Device (PLD) and a synthesis approach are proposed. Our PLD is derived from traditional Programmable Logic Array (PLA). The key extension is that programmable AND devices in PLA is replaced by Look-Up Tables (LUTs). A series of cascaded LUTs in the array can generate more complex terms, which we call generalized complex terms (GCTs), than product terms. In order to utilize the capability, a synthesis approach to map a given function into the array is also proposed. Our approach generates a expression of the sum of GCTs aiming to minimize the number of terms. A number of experimental results demonstrate that the number of terms for our PLD generated by our approach is 14.9% fewer than that by an existing approach. We design our PLD based on a fundamental unit named nGCT cell which can be used as LUTs in multiple sizes or random access memories. Implementation of the PLD based on a fundamental unit named nGCT cell which can be used as LUTs or random access memories is also described.

In this paper, a LSI design for video encoder and decoder for H.263+ video compression is presented. LSI operates under clock frequency of 27 MHz to compress QCIF (176144 pixels) at the frame rate of 30 frame per second. The core size is 4.6 4.6 mm2 in a 0.35 µm process. The architecture is based on bus connected heterogeneous dedicated modules, named as System-MSPA architecture. It employs the fast and small-chip-area dedicated modules in lower level and controls them by employing the slow and flexible programmable device and an external DRAM. Design results in success to achieve real time encoder in quite compact size without losing flexibility and expand ability. Real time emulation and easy test capability with external PC is also implemented.

As LSIs are two-dimensional structures, the number of external pins increases at a lower rate than the corresponding increase in the number of gates on the LSI. Therefore, the number of flip-flops on a scan path increases as the density of gates on LSIs rises, resulting in longer test application times. In this paper, three novel DFT strategies aimed at reducing test application time are proposed. DFT strategy 1 is a full scan design method with test point insertion, DFT strategy 2 is a partial scan design method, and DFT strategy 3 is a partial scan design method with test point insertion. Experimental results show that these DFT strategies reduced the test application times by 45% to 82% compared with conventional full scan design methods.

This paper presents an automatic synthesis method of active analog circuits that uses evolutionary search and employs some topological features of analog integrated circuits. Our system firstly generates a set of circuits at random, and then evolves their topologies and device sizing to fit an environment which is formed by the fitness function translated from the electrical specifications of the circuit. Therefore expert knowledge about circuit topologies and sizing are not needed. The capability of this method is demonstrated through experiments of automatic synthesis of CMOS operational amplifiers.

Simulation based education and training, especially wargame simulations, are being used widely in the field of defense modeling and in simulation communities. In order to efficiently train students and trainees, the wargame simulations must have both high performance and high fidelity. In this paper, we discuss design and implementation issues for a prototype of a parallel and distributed wargame simulation system. This wargame simulation system is based on High Level Architecture (HLA) and employs some optimization to achieve both high performance and high fidelity in the simulation system. The results show that the proposed optimization method is effective when optimization is applied to 93.5% or less of the moving objects (PFs) within the range of detection (RofD) of both the red and blue teams. Specifically, when each team has 1000 PFs we found that if the percentage of PFs within RofD is less than 50% for both teams, our method is over two times better than for the situation where there is no optimization.

The effect of Unbalanced-Magnetic-Pull (UMP) on vibration and run-outs has become stringent in the design for high performance HDD spindle motors. In this paper, reducing the UMP and also minimizing its variability for an 8-pole 9-slot spindle motor to achieve robustness in the performance is described and illustrated using novel robust design methods. A screening experiment identifies the key design parameters. Using Design of experiment (DOE) and Analysis of Variance (ANOVA), the parameter design reduces the amplitude of UMP and minimizes its variability by product parameter optimization. The tolerance design improves the quality by tightening tolerances on product or process parameters to reduce the performance variation. The optimal design process includes considerations of manufacturing and process noises, such as manufacturing tolerances for the slot opening and variation of the rotor magnet magnetization distribution due to the magnetization fixture and process. The optimal design procedure is briefly introduced and the results are presented.

Analysis of a novel folded loop antenna for handset is described along with the advanced design concept for handset antennas. The design concept shown in this paper meets the foremost requirement for handset antennas such as (1) small size and yet (2) has capability of mitigating degradation of antenna performance due to the body effect, and (3) of reducing SAR value in the human head at the handset talk position, in addition to the indispensable requirements for handset antennas such as (4) low profile, and (5) light weight. The technology applied is to make this antenna (a) an integrated structure, which is a typical application of the fundamental concept of making antennas small and (b) a balanced structure which has been proved to be very effective to satisfy the requirements (2) and (3). The antenna is essentially a two-wire transmission line, folded at about a quarter-wavelength to form a half-wave folded dipole, and yet appears to be a loop of one-wavelength. It does not have really a balanced structure, as is fed with an unbalanced line; however, the antenna structure itself can eliminate the unbalanced current flow on the feed line as in the balanced antenna system. Both theoretical and experimental analyses have been shown and the usefulness of the antenna is discussed. This paper may suggest the advanced technology and design concept that will be applied to the development of handset antennas toward the future.

We present a design strategy to reduce power demands in application-specific, heterogeneous multiprocessor systems with interdependent subtasks. This power reduction scheme can be used with a randomised search such as a genetic algorithm where multiple trial solutions are tested. The scheme is applied to each trial solution after allocation and scheduling have been performed. Power savings are achieved by equally expanding each processor's execution time with a corresponding reduction in their respective operating voltage. Lowest cost solutions achieve average reductions of 24% while minimum power solutions average 58%.

Systems comprised of multiple interacting mobile agents provide an alternate network computing paradigm that integrates remote data access, message exchange and migration; which up until now have largely been considered independently. On the surface distributed systems design could be helped by a complete specification of the different interaction patterns, however the number of possible designs in any large scale system undergoes a combinatorial explosion. As a consequence this paper focuses on basic one-to-one agent interactions, or paradigms, which can be used as building blocks; allowing larger system characteristics and performance to be understood in terms of their combination. This paper defines three basic agent paradigms and presents associated performance models. The paradigms are evaluated quantitatively in terms of network traffic, overall processing time and size of memory used, in the context of a distributed DB system developed using the Bee-gent Agent Framework. Comparison of the results and models illustrates the performance trade-off for each paradigm, which are not represented in the models, and some implementation issues of agent frameworks. The paper ends with a case study of how to select an appropriate paradigm.

As Information Technology progresses, our daily lives are getting "connected" more and more. At the same time, however, problems are appearing. The center of these problems can be captured as the "Communication Overflow. " To cope with such problems, we propose an approach that tries to provide a communication environment that assists users in managing their communication activities. The key notion of this approach is to enhance the "Awareness of Connectedness. " Here, agents which are suggestive of awareness of connectedness play an important role. In this paper, we describe the key notion and introduce a brief road-map towards the environment for the awareness of connectedness. Two candidate tools for the environment are described. The first one is a visualization tool for communication media that provides feedback of users' communication activities. Its purpose is to enhance the awareness for communication. The second tool is a simple, intuitive interactive media that exchanges the statuses of users. It is an alternative network communication media that might be suitable for very light-weight, almost-acknowledge-only communication mode. Some results on an experiment of these two tools are also reported.

The formulation of the process of analog system design has been done on the basis of the control theory application. This approach generalizes the design process and produces different design trajectories inside the same optimization procedure. The problem of the optimal design algorithm construction is defined as the minimal-time problem of the control theory. The main equations for the proposed design methodology were elaborated. These equations include the special control functions that are introduced artificially to generalize the design problem. Optimal dependencies of the control functions give the possibility to reduce the total computer design time. This idea was tested with different optimization algorithms of the design process. Numerical results of some simple electronic circuit design demonstrate the efficiency of the proposed approach. These examples show that the traditional design strategy is not time-optimal and the potential computer time gain of the optimal design strategy increases when the size and complexity of the system increase.

Technology scaling will become difficult due to power wall. On the other hand, future computer and communications technology will require further reduction in power dissipation. Since no new energy efficient device technology is on the horizon, low power CMOS design should be challenged. This paper discusses what and how much designers can do for CMOS power reduction.

A knowledge gap between network operators and system developers in Network Management System (NMS) construction has widened. This has been caused by an expansion of supported business processes and increasingly sophisticated network management functions. This gap makes system development costly and time consuming. Function development, led by operators, is a promising solution to the problems caused by the gap. This type of development should not require an operator to know how to develop NMS. Standard objects may be used to meet this requirement and save time and the cost of NMS construction. However, they are not sufficient to design functions supporting some tasks that are for providing custom services. In this paper, we propose a partial extension package, composed of several object classes. This package is attached to the standard objects to design a custom function. Information processing in a new function can be added, and easily modified, using this package. This package specifies states that invoke the information processing. It also includes objects that add new data without changing standard objects. It makes use of several design patterns in order to weaken coupling to the standard objects. We have applied this package to two programs. One plans maintenance tasks schedules, the other sets threshold values for quality of service. We made use of software metrics to measure their performance in terms of flexibility. The results show that the proposed package continues to make it possible to reuse the standard objects, and makes it easy to modify the behavior of a new function.

We propose the architecture of efficiently and flexibly extensible solver system for electromagnetic wave simulations, that can load multi kinds of schemes such as Finite-Difference Time-Domain (FDTD) scheme, Finite Element Method (FEM), and a circuit simulator, with various boundary conditions in the system. Object-oriented approach is a promising method for efficient development of the flexible simulator. The primary object in the architecture is found through our object-oriented analysis as decomposed "region" from whole the simulation space. The decomposed region is considered to be the stage on which the electromagnetic fields play under the local rules. Developers who will extend the functionality of the system can add new classes inherited from the abstract classes in our design depending on the grid structure, the scheme, or the boundary processing method.

Although Maxwell's equations have been known for over 100 years, it was not until the last decade that they have seen regular use in applied high frequency design. The availability of sufficient computer processing capability is only part of the reason Maxwell's equations now enjoy regular application. Other developments requiring considerable effort are needed as well. These include increased attention to robustness, software testing, ease of use, portability, integration with other tools, and support. These developments are detailed in this paper.