Recent years have seen a general resurgence of interest in analog signal processing and computing architectures. In addition, extensive theoretical and experimental literature on chaos and analog chaotic oscillators exists. One peculiarity of these circuits is the ability to generate, despite their structural simplicity, complex spatiotemporal patterns when several of them are brought towards synchronization via coupling mechanisms. While by no means a systematic survey, this paper provides a personal perspective on this area. After briefly covering design aspects and the synchronization phenomena that can arise, a selection of results exemplifying potential applications is presented, including in robot control, distributed sensing, reservoir computing, and data augmentation. Despite their interesting properties, the industrial applications of these circuits remain largely to be realized, seemingly due to a variety of technical and organizational factors including a paucity of design and optimization techniques. Some reflections are given regarding this situation, the potential relevance to discontinuous innovation in analog circuit design of chaotic oscillators taken both individually and as synchronized networks, and the factors holding back the transition to higher levels of technology readiness.

A 0.13mJ/prediction with 68.6% accuracy wired-logic deep neural network (DNN) processor is developed in a single 16-nm field-programmable gate array (FPGA) chip. Compared with conventional von-Neumann architecture DNN processors, the energy efficiency is greatly improved by eliminating DRAM/BRAM access. A technical challenge for conventional wired-logic processors is the large amount of hardware resources required for implementing large-scale neural networks. To implement a large-scale convolutional neural network (CNN) into a single FPGA chip, two technologies are introduced: (1) a sparse neural network known as a non-linear neural network (NNN), and (2) a newly developed raster-scan wired-logic architecture. Furthermore, a novel high-level synthesis (HLS) technique for wired-logic processor is proposed. The proposed HLS technique enables the automatic generation of two key components: (1) Verilog-hardware description language (HDL) code for a raster-scan-based wired-logic processor and (2) test bench code for conducting equivalence checking. The automated process significantly mitigates the time and effort required for implementation and debugging. Compared with the state-of-the-art FPGA-based processor, 238 times better energy efficiency is achieved with only a slight decrease in accuracy on the CIFAR-100 task. In addition, 7 times better energy efficiency is achieved compared with the state-of-the-art network-optimized application-specific integrated circuit (ASIC).

Webpage texts are often emphasized by decorations such as bold, italic, underline, and text color using HTML (HyperText Markup Language) tags and CSS (Cascading Style Sheets). However, users with visual impairment often struggle to recognize decorations appropriately because most screen readers do not read decorations appropriately. To overcome this limitation, we propose a method to read emphasized texts by changing the reading voice parameters of a screen reader and adding sound effects. First, the strong emphasis types and reading voices are investigated. Second, the intensity of the emphasis type is used to calculate a score. Then the score is used to assign the reading method for the emphasized text. Finally, the proposed method is evaluated by users with and without visual impairment. The proposed method can convey emphasized texts, but future improvements are necessary.

A method for bandwidth enhancement of radar cross section (RCS) reduction by metasurfaces was studied. Scattering cancellation is one of common methods for reducing RCS of target scatterers. It occurs when the wave scattered by the target scatterer and the wave scattered by the canceling scatterer are the same amplitude and opposite phase. Since bandwidth of scattering cancellation is usually narrow, we proposed the bandwidth enhancement method using metasurfaces, which can control the frequency dependence of the scattering phase. We designed and fabricated a metasurface composed of a patch array on a grounded dielectric substrate. Numerical and experimental evaluations confirmed that the metasurface enhances the bandwidth of 10dB RCS reduction by 52% bandwidth ratio of the metasurface from 34% bandwidth ratio of metallic cancelling scatterers.

In recent years, to meet strict time-to-market constraints, it has become difficult for only one semiconductor design company to design a VLSI. Thus, design companies purchase IP cores from third-party IP vendors and design only the necessary parts. On the other hand, since IP cores have the disadvantage that copyright infringement can be easily performed, logic locking has to be applied to them. Functional logic locking methods using TTLock are resilient to SAT attacks however vulnerable to FALL attacks. Additionally, it is difficult to design logic locking based on TTLock at the gate level. This paper proposes a logic locking method, CRLock, based on SAT attack and FALL attack resistance at the register transfer level. The CRLock is a logic locking method for controllers at RTL in which the designer selects a protected input pattern and modifies the controller based on the protection input pattern. In experimental results, we applied CRLock to MCNC'91 benchmark circuits and showed that all circuits are resistant to SAT and FALL attacks.

We have realized a design automation platform of hardware accelerator for pairing operation over multiple elliptic curve parameters. Pairing operation is one of the fundamental operations to realize functional encryption. However, known as a computational complexity-heavy algorithm. Also because there have been not yet identified standard parameters, we need to choose curve parameters based on the required security level and affordable hardware resources. To explore this design optimization for each curve parameter is essential. In this research, we have realized an automated design platform for pairing hardware for such purposes. Optimization results show almost equivalent to those prior-art designs by hand.

This paper considers the problem of balancing traceability and anonymity in designated verifier signatures (DVS), which are a kind of group-oriented signatures. That is, we propose claimable designated verifier signatures (CDVS), where a signer is able to claim that he/she indeed created a signature later. Ordinal DVS does not provide any traceability, which could indicate too strong anonymity. Thus, adding claimability, which can be seen as a sort of traceability, moderates anonymity. We demonstrate two generic constructions of CDVS from (i) ring signatures, (non-ring) signatures, pseudorandom function, and commitment scheme, and (ii) claimable ring signatures (by Park and Sealfon, CRYPTO'19).

This paper proposes a network design model, considering data consistency for a delay-sensitive distributed processing system. The data consistency is determined by collating the own state and the states of slave servers. If the state is mismatched with other servers, the rollback process is initiated to modify the state to guarantee data consistency. In the proposed model, the selected servers and the master-slave server pairs are determined to minimize the end-to-end delay and the delay for data consistency. We formulate the proposed model as an integer linear programming problem. We evaluate the delay performance and computation time. We evaluate the proposed model in two network models with two, three, and four slave servers. The proposed model reduces the delay for data consistency by up to 31 percent compared to that of a typical model that collates the status of all servers at one master server. The computation time is a few seconds, which is an acceptable time for network design before service launch. These results indicate that the proposed model is effective for delay-sensitive applications.

In this paper, we investigate the evolution of an optical network architecture and discuss the future direction of research on optical network design and control. We review existing research on optical network design and control and present some open challenges. One of the important open challenges lies in multilayer resource optimization including IT and optical network resources. We propose an adaptive joint optimization method of IT resources and optical spectrum under time-varying traffic demand in optical networks while avoiding an increase in operation cost. We formulate the problem as mixed integer linear programming and then quantitatively evaluate the trade-off relationship between the optimality of reconfiguration and operation cost. We demonstrate that we can achieve sufficient network performance through the adaptive joint optimization while suppressing an increase in operation cost.

In this paper we obtain a new method to compute the correlation values of two arbitrary sequences defined by a mapping from F4n to F4. We apply this method to demonstrate that the usual nonbinary maximal length sequences have almost ideal correlation under the canonical complex correlation definition and investigate some decimations giving good cross correlation. The techniques we develop are of independent interest for future investigation of sequence design and related problems, including Boolean functions.

A set consisting of K subsets of Msequences of length L is called a complementary sequence set expressed by A(L, K, M), if the sum of the out-of-phase aperiodic autocorrelation functions of the sequences within a subset and the sum of the cross-correlation functions between the corresponding sequences in any two subsets are zero at any phase shift. Suehiro et al. first proposed complementary set A(Nn, N, N) where N and n are positive integers greater than or equal to 2. Recently, several complementary sets related to Suehiro's construction, such as N being a power of a prime number, have been proposed. However, there is no discussion about their inclusion relation and properties of sequences. This paper rigorously formulates and investigates the (generalized) logic functions of the complementary sets by Suehiro et al. in order to understand its construction method and the properties of sequences. As a result, it is shown that there exists a case where the logic function is bent when n is even. This means that each series can be guaranteed to have pseudo-random properties to some extent. In other words, it means that the complementary set can be successfully applied to communication on fluctuating channels. The logic functions also allow simplification of sequence generators and their matched filters.

Mobility as a Service (MaaS) is a smart mobility model that integrates mobility services to deliver transportation needs through a single interface, offering users flexible and personalizd mobility. This paper presents a structural approach for developing a MaaS system architecture under Autonomous Transportation Systems (ATS), which is a new transition from the Intelligent Transportation Systems (ITS) with emerging technologies. Five primary components, including system elements, user needs, services, functions, and technologies, are defined to represent the system architecture. Based on the components, we introduce three architecture elements: functional architecture, logical architecture and physical architecture. Furthermore, this paper presents an evaluation process, links the architecture elements during the process and develops a three-layer structure for system performance evaluation. The proposed MaaS system architecture design can help the administration make services planning and implement planned services in an organized way, and support further technical deployment of mobility services.

Binary Neural Networks (BNN) have binarized neuron and connection values so that their accelerators can be realized by extremely efficient hardware. However, there is a significant accuracy gap between BNNs and networks with wider bit-width. Conventional BNNs binarize feature maps by static globally-unified thresholds, which makes the produced bipolar image lose local details. This paper proposes a multi-input activation function to enable adaptive thresholding for binarizing feature maps: (a) At the algorithm level, instead of operating each input pixel independently, adaptive thresholding dynamically changes the threshold according to surrounding pixels of the target pixel. When optimizing weights, adaptive thresholding is equivalent to an accompanied depth-wise convolution between normal convolution and binarization. Accompanied weights in the depth-wise filters are ternarized and optimized end-to-end. (b) At the hardware level, adaptive thresholding is realized through a multi-input activation function, which is compatible with common accelerator architectures. Compact activation hardware with only one extra accumulator is devised. By equipping the proposed method on FPGA, 4.1% accuracy improvement is achieved on the original BNN with only 1.1% extra LUT resource. Compared with State-of-the-art methods, the proposed idea further increases network accuracy by 0.8% on the Cifar-10 dataset and 0.4% on the ImageNet dataset.

When mission-critical applications are provided over a network, high availability is required in addition to a low delay. This paper proposes a multi-homing network design model, named MHND, that achieves low delay, high availability, and the order guarantee of events. MHND maintains the event occurrence order with a multi-homing configuration using conservative synchronization. We formulate MHND as an integer linear programming problem to minimize the delay. We prove that the distributed server allocation problem with MHND is NP-complete. Numerical results indicate that, as a multi-homing number, which is the number of servers to which each user belongs, increases, the availability increases while increasing the delay. Noteworthy, two or more multi-homing can achieve approximately an order of magnitude higher availability compared to that of conventional single-homing at the expense of a delay increase up to two times. By using MHND, flexible network design is achieved based on the acceptable delay in service and the required availability.

Mission-critical monitoring services, such as finding criminals with a monitoring camera, require rapid detection of newly updated data, where suppressing delay is desirable. Taking this direction, this paper proposes a network design scheme to minimize this delay for monitoring services that consist of Internet-of-Things (IoT) devices located at terminal endpoints (TEs), databases (DB), and applications (APLs). The proposed scheme determines the allocation of DB and APLs and the selection of the server to which TE belongs. DB and APL are allocated on an optimal server from multiple servers in the network. We formulate the proposed network design scheme as an integer linear programming problem. The delay reduction effect of the proposed scheme is evaluated under two network topologies and a monitoring camera system network. In the two network topologies, the delays of the proposed scheme are 78 and 80 percent, compared to that of the conventional scheme. In the monitoring camera system network, the delay of the proposed scheme is 77 percent compared to that of the conventional scheme. These results indicate that the proposed scheme reduces the delay compared to the conventional scheme where APLs are located near TEs. The computation time of the proposed scheme is acceptable for the design phase before the service is launched. The proposed scheme can contribute to a network design that detects newly added objects quickly in the monitoring services.

Today's electronic devices must meet many requirements, such as those related to performance, limits to the radiated electromagnetic field, size, etc. For such a design, the requirement is to have a solution that simultaneously meets multiple objectives that sometimes include conflicting requirements. In addition, it is also necessary to consider uncertain parameters. This paper proposes a new combination of statistical analysis using the Polynomial Chaos (PC) method for dealing with the random and multi-objective satisfactory design using the Preference Set-based Design (PSD) method. The application in this paper is an Electromagnetic Interference (EMI) filter for a practical case, which includes plural element parameters and uncertain parameters, which are resistors at the source and load, and the performances of the attenuation characteristics. The PC method generates simulation data with high enough accuracy and good computational efficiency, and these data are used as initial data for the meta-modeling of the PSD method. The design parameters of the EMI filter, which satisfy required performances, are obtained in a range by the PSD method. The authors demonstrate the validity of the proposed method. The results show that applying a multi-objective design method using PSD with a statistical method using PC to handle the uncertain problem can be applied to electromagnetic designs to reduce the time and cost of product development.

Recent years have seen a decline in the art of analog IC design even though analog interface and analog signal processing remain just as essential as ever. While there are many contributing factors, four specific pressures which contribute the most to the loss of creativity and innovation within analog practice are examined: process evolution, risk aversion, digitally assisted analog, and corporate culture. Despite the potency of these forces, none are found to be insurmountable obstacles to reinvigorating the industry. A more creative future is within our reach.

Reducing on-chip microwave crosstalk is crucial for semiconductor spin qubit integration. Toward crosstalk reduction and qubit integration, we investigate on-chip microwave crosstalk for gate electrode pad designs with (i) etched trenches between contact pads or (ii) contact pads with reduced sizes. We conclude that the design with feature (ii) is advantageous for high-density integration of semiconductor qubits with small crosstalk (below -25 dB at 6 GHz), favoring the introduction of flip-chip bonding.

Recently, many AI-aided layout design systems are developed to reduce tedious manual intervention based on deep learning. However, most methods focus on a specific generation task. This paper explores a challenging problem to obtain multiple layout design generation (LDG), which generates floor plan or urban plan from a boundary input under a unified framework. One of the main challenges of multiple LDG is to obtain reasonable topological structures of layout generation with irregular boundaries and layout elements for different types of design. This paper formulates the multiple LDG task as an image-to-image translation problem, and proposes a conditional generative adversarial network (GAN), called LDGAN, with adaptive modules. The framework of LDGAN is based on a generator-discriminator architecture, where the generator is integrated with conditional convolution constrained by the boundary input and the attention module with channel and spatial features. Qualitative and quantitative experiments were conducted on the SCUT-AutoALP and RPLAN datasets, and the comparison with the state-of-the-art methods illustrate the effectiveness and superiority of the proposed LDGAN.

This paper addresses an observer-design method only using data. Usually, the observer requires a mathematical model of a system for state prediction and observer gain calculation. As an alternative to the model-based prediction, the proposed predictor calculates the states using a linear combination of the given data. To design the observer gain, the data which represent dual systems are derived from the data which represent the original system. Linear matrix inequalities that depend on data of the dual system provides the observer gains.