Due to the increasing need for low-power circuits in mobile applications, numerous leakage and performance optimization techniques are being used in modern ICs. In the present paper, we propose a novel transistor-level technique to reduce leakage current while maintaining drive current. By slightly increasing the channel length at the edge of a device that exploits the edge effect, a leakage-optimized transistor can be produced. By using TCAD simulations, we analyze edge-length-biased transistors and then propose the optimal transistor shape for minimizing Ioff with the same or higher Ion current. Results show that by replacing all standard cells with their leakage-optimized counterparts, we can save up to 17% of the leakage in average for a set of benchmark circuits.

In this paper, we introduce generalized feed-forward shift registers (GF2SR) to apply them to secure and testable scan design. Previously, we introduced SR-equivalents and SR-quasi-equivalents which can be used in secure and testable scan design, and showed that inversion-inserted linear feed-forward shift registers (I2LF2SR) are useful circuits for the secure and testable scan design. GF2SR is an extension of I2LF2SR and the class is much wider than that of I2LF2SR. Since the cardinality of the class of GF2SR is much larger than that of I2LF2SR, the security level of scan design with GF2SR is much higher than that of I2LF2SR. We consider how to control/observe GF2SR to guarantee easy scan-in/out operations, i.e., state-justification and state-identification problems are considered. Both scan-in and scan-out operations can be overlapped in the same way as the conventional scan testing, and hence the test sequence for the proposed scan design is of the same length as the conventional scan design. A program called WAGSR (Web Application for Generalized feed-forward Shift Registers) is presented to solve those problems.

With the rapid expansion of vector data model application to digital content such as drawings and digital maps, the security and retrieval for vector data models have become an issue. In this paper, we present a vector data-hashing algorithm for the authentication, copy protection, and indexing of vector data models that are composed of a number of layers in CAD family formats. The proposed hashing algorithm groups polylines in a vector data model and generates group coefficients by the curvatures of the first and second type of polylines. Subsequently, we calculate the feature coefficients by projecting the group coefficients onto a random pattern, and finally generate the binary hash from binarization of the feature coefficients. Based on experimental results using a number of drawings and digital maps, we verified the robustness of the proposed hashing algorithm against various attacks and the uniqueness and security of the random key.

This paper presents a method of designing transmission line couplers (TLCs) and a mixer-based receiver for dicode partial response communications. The channel design method results in the optimum TLC design. The receiver with mixers and DC balancing circuits reduces the threshold control circuits and digital circuits to decode dicode partial response signals. Our techniques enable low inter-symbol interference (ISI) dicode partial response communications without three level decision circuits and complex threshold control circuits. The techniques were evaluated in a simulation with an EM solver and a transistor level simulation. The circuit was designed in the 90-nm CMOS process. The simulation results show 12-Gb/s operation and 52mW power consumption at 1.2V.

This paper presents a low-power LDPC decoder that can be used in Multimedia Wireless Sensor Networks. Three low power design techniques are proposed in the decoder design: a layered decoding algorithm, a modified Benes network and a modified memory bypassing scheme. The proposed decoder is implemented in TSMC 0.13 µm, 1.2 V CMOS process. Experiments show that when the clock frequency is 32 MHz, the power consumption of the proposed decoder is 38.4 mW, the energy efficiency is 53.3 pJ/bit/ite and the core area is 1.8 mm2.

This paper presents an adaptive cache architecture for wide-range reliable low-voltage operations. The proposed associativity-reconfigurable cache consists of pairs of cache ways so that it can exploit the recovery feature of the novel 7T/14T SRAM cell. Each pair has two operating modes that can be selected based upon the required voltage level of current operating conditions: normal mode for high performance and dependable mode for reliable low-voltage operations. We can obtain reliable low-voltage operations by application of the dependable mode to weaker pairs that cannot operate reliably at low voltages. Meanwhile leaving stronger pairs in the normal mode, we can minimize performance losses. Our chip measurement results show that the proposed cache can trade off its associativity with the minimum operating voltage. Moreover, it can decrease the minimum operating voltage by 140 mV achieving 67.48% and 26.70% reduction of the power dissipation and energy per instruction. Processor simulation results show that designing the on-chip caches using the proposed scheme results in 2.95% maximum IPC losses, but it can be chosen various performance levels. Area estimation results show that the proposed cache adds area overhead of 1.61% and 5.49% in 32-KB and 256-KB caches, respectively.

This paper proposes an ASIC design support tool set for non-pipelined asynchronous circuits with bundled-data implementation. This tool set consists of seven tools to automate design processes of bundled-data implementation such as the generation of design constraints, timing verification, and delay adjustment considering a given latency constraint. With the proposed design flow which combines the proposed tool set and commercial CAD tools, most of design processes from an RTL model is fully automated. In the experiments, to show the effectiveness of energy consumption in bundled-data implementation compared to synchronous counterpart, this paper synthesizes several circuits with a latency constraint which is generated from the synchronous counterpart with the minimum clock cycle time.

This paper presents a novel decision feedback equalizer (DFE) with block delay detection for the joint transceiver design that uses channel state information (CSI). The block delay detection in the proposed DFE offers a degree of freedom for optimizing the precoder of the transmitter, provided the transmission power is constrained. In the proposed DFE, the feedforward matrix is devised to enable a block-based equalizer that can be cooperated with an intrablock decision feedback equalizer for suppressing the intersymbol interference (ISI) for the transmitted block with a certain block delay. In this design, the interblock interference (IBI) for the delay block is eliminated in advance by applying the recently developed oblique projection framework to the implementation of the feedforward matrix. With knowledge of full CSI, the block delay and the associated block-based precoder are jointly designed such that the average bit-error-rate (BER) is minimized, subject to the transmission power constraint. Separate algorithms are derived for directly determining the BER-minimized block delays for intrablock minimum mean-squared error (MMSE) and zero-forcing (ZF) equalization criteria. Theoretical derivations indicate that the proposed MMSE design simultaneously maximize the Gaussian mutual information of a transceiver, even under the cases of existing IBI. Simulation results validate the proposed DFE for devising an optimum transceiver with CSI, and show the superior BER performance of the optimized transceiver using proposed DFE. Relying on analytic results and simulation cases also builds a sub-optimum MMSE design of the proposed DFE using the BER-minimized block delay for ZF criterion, which exhibits almost identical BER performance as the proposed MMSE design in most of the signal-to-noise ratio (SNR) range.

Let Gs=(Vs, Es) be a simple connected graph. A vertex v ∈ Vs is an articulation vertex if deletion of v and its incident edges from Gs disconnects the graph into at least two connected components. Finding all articulation vertices of a given graph is called the articulation vertex problem. A vertex u ∈ Vs is called a hinge vertex if there exist any two vertices x and y in Gs whose distance increase when u is removed. Finding all hinge vertices of a given graph is called the hinge vertex problem. These problems can be applied to improve the stability and robustness of communication network systems. In this paper, we propose linear time algorithms for the articulation vertex problem and the hinge vertex problem of circular permutation graphs.

This paper presents analysis and design of passive RC polyphase filters (RCPFs) in tutorial style. Single-phase model of a single-stage RCPF is derived, and then, multi-stage RCPFs are analyzed and obtained some restrictions for realizable poles and zeros locations of RCPFs. Exact design methods of RCPFs with equal ripple type, and Butterworth type responses are explained for transfer function design and element value design along with some design examples.

This letter describes the design methodology for reduced reconfigurable logic circuits based on double gate carbon nanotube field effect transistors (DG-CNTFETs) with ambipolar propoerty. Ambipolar Binary Decision Diagram (Am-BDD) which represents the cornerstone for automatic pass transistor logic (PTL) synthesis flows of ambipolar devices was utilized to build DG-CNTFET based n-input reconfigurable cells in the conventional approach. The proposed method can reduce the number of ambipolar devices for 2-inputs reconfigurable cells, incorporating the simple Boolean algebra in the Am-BDD compared with the conventional approach. As a result, the static 2-inputs reconfigurable circuit with 16 logic functions can be synthesized by using 8 DG-CNTFETs although the previous design method needed 12 DG-CNTFETs for the same purpose.

In this paper, a new bandwidth allocation scheme is proposed based on the Mechanism Design (MD); MD is a branch of game theory that stimulates rational users to behave cooperatively for a global goal. The proposed scheme consists of bandwidth adaptation, call admission control and pricing computation algorithms to improve network performance. These algorithms are designed based on the adaptive online approach and work together to maximize bandwidth efficiency economically. A simulation shows that the proposed scheme can satisfy contradictory requirements and so provide well-balanced network performance.

This paper presents a high-efficiency boost converter with voltage clamp function. It clarifies how to design the inductance of the coupled inductor used in the converter, and derives characteristic equations that associate the fluctuation in the input voltage with the output ripple current. For this converter, a theoretical analysis, simulation and experimentation (prototype output: 98 V, 13 A) are performed. As a result, the converter is achieved high efficiency (Maximum efficiency: 98.1%) in the rated output condition, indicating that the voltage stress on the switching power semiconductors can be mitigated by using the voltage clamp function. And it is verified that the snubber circuit can be eliminated in the switching power semiconductors. In addition, the theoretical output ripple current characteristics are corresponded well with simulation and experimental results, and the validity of the design method is proved.

Product return is a critical but controversial issue. To deal with such a vague return problem, businesses must improve their information transparency in order to administrate the product return behaviour of their end users. This study proposes an intelligent return administration expert system (iRAES) to provide product return forecasting and decision support for returned product administration. The iRAES consists of two intelligent agents that adopt a hybrid data mining algorithm. The return diagnosis agent generates different alarms for certain types of product return, based on forecasts of the return possibility. The return recommender agent is implemented on the basis of case-based reasoning, and provides the return centre clerk with a recommendation for returned product administration. We present a 3C-iShop scenario to demonstrate the feasibility and efficiency of the iRAES architecture. Our experiments identify a particularly interesting return, for which iRAES generates a recommendation for returned product administration. On average, iRAES decreases the effort required to generate a recommendation by 70% compared to previous return administration systems, and improves performance via return decision support by 37%. iRAES is designed to accelerate product return administration, and improve the performance of product return knowledge management.

This study examines the robustness of image quality factors in various types of environment illumination using a parameter design in the field of quality engineering. Experimental results revealed that image quality factors are influenced by environment illuminations in the following order: minimum luminance, maximum luminance and gamma.

Capacitor charging modeling efficiently and accurately represents power consumption current of CMOS digital circuits and actualizes co-simulation of AC power noise including the interaction with on-chip and on-board integrated power delivery network (PDN). It is clearly demonstrated that the AC power noise is dominantly characterized by the frequency-dependent impedance of PDN and also by the operating frequency of circuits as well. A 65 nm CMOS chip exhibits the AC power noise components in substantial relation with the parallel resonance of the PDN seen from on-chip digital circuits. An on-chip noise monitor measures in-circuit power supply voltage, while a near-field magnetic probing derives on-board power supply current. The proposed co-simulation well matches the power noise measurements. The proposed AC noise co-simulation will be essentially applicable in the design of PDNs toward on-chip power supply integrity (PSI) and off-chip electromagnetic compatibility (EMC).

An analytical performance evaluation model is presented in this paper. A time-splitting transmitter circuit employing a selectively activated flip-driver (SAFD) is presented and its performance is estimated by the new model. The optimal partitioning method which maximizes the performance of a given bus-invert (BI) coding circuit is also presented. When a bus is optimally partitioned, an ordinary BI circuit can reduce the number of bus transitions by about 25%, while an SAFD circuit can remove about 35% of them. The newly developed method is verified by simulations whose results correspond very well to the values predicted by the model.

We propose optical path routing and frequency slot assignment algorithms that can make the best use of elastic optical paths and the capabilities of distance adaptive modulation. Due to the computational difficulty of the assignment problem, we develop algorithms for 1+1 dedicated/1:1 shared protected ring networks and unprotected mesh networks to that fully utilize the characteristics of the topologies. Numerical experiments elucidate that the introduction of path elasticity and distance adaptive modulation significantly reduce the occupied bandwidth.

With the development of Global Navigation Satellite System (GNSS), the amount of related research is growing rapidly in China. A lot of accomplishments have been achieved in all branches of the satellite navigation field, especially motivated by the BeiDou Program. In this paper, the current status, technologies and developments in satellite positioning and navigation in China are introduced. Firstly, an overview and update of the BeiDou Program is presented, known as the three-step development strategy for different services. Then signal design for the BeiDou system is discussed, including the generation of pseudo-random noise (PRN) codes for currently available signal B1, and the investigation of a new signal modulation scheme for interoperability at open frequency B1C. The B1C signal should comply to Multiplexed Binary Offset Carrier (MBOC) constrains, and a modulation called Quadrature Multiplexed BOC (QMBOC) is presented, which is equivalent to time-multiplexed BOC (TMBOC) for GPS and composite BOC (CBOC) for Galileo, while overcomes the drawback of CBOC. Besides, the inter and intra system compatibility is discussed, based on the effective C/N0 proposed by International Telecommunication Union (ITU). After that, receiver technologies in challenging environments are introduced, such as weak signal acquisition and assisted GNSS (A-GNSS). Moreover, a method of ambiguity mitigation for adaptive digital beam forming (ADBF) in large spacing antenna arrays is proposed, by which interference suppression is available. Furthermore, cutting edge technologies are brought in, including seamless navigation for indoor and outdoor, and collaborative navigation. After all, GNSS applications in China for industry and daily life are shown, as well as the market prospection.

In this paper, we propose a hardware architecture of high-speed sorted QR decomposition for 44 MIMO wireless communication systems. QR decomposition (QRD) is commonly used in many MIMO detection algorithms. In particular, sorted QR decomposition (SQRD) is the advanced algorithm to improve MIMO detection performance. We design an SQRD hardware architecture by using a modified Gram-Schmidt algorithm with pipelining and recursive processing. In addition, we propose an extended architecture which can decompose an augmented channel matrix for MMSE MIMO detection. These architecture can be applied in high-throughput MIMO-OFDM system such as IEEE802.11n which supports data throughput of up to 600 Mbps. We implement the proposed SQRD architecture and the proposed MMSE-SQRD architecture with 179k and 334k gates in 90 nm CMOS technology. These proposed design can achieve a high performance of up to 40.8 and 50.0 million 44 SQRD operations per second with the maximum operating frequency of 245 and 300 MHz.