The present paper introduces a new approach to the construction of a sequence set with a zero-correlation zone (ZCZ), which is referred to as a ZCZ sequence set. The proposed sequence construction generates a ZCZ sequence set from a ZCZ sequence set. The proposed method can generate an almost optimal ZCZ sequence set, the member size of which approaches the theoretical bound, when an almost optimal ZCZ sequence is used for the sequence construction. The proposed sequence set consists of NO subsets, where a ZCZ sequence set Z(LO, NO, ZO is used in sequence construction. The correlation function of the sequences of a pair of different subsets, referred to as the inter-subset correlation function, has a ZCZ with a width that is about times that of the correlation function of sequences of the same subset (intra-subset correlation function) for integers Λ ≥ 1, T, and m ≥ 0. Wide inter-subset zero-correlation enables improved performance during application of the proposed sequence set.

With the development of Global Navigation Satellite System (GNSS), the amount of related research is growing rapidly in China. A lot of accomplishments have been achieved in all branches of the satellite navigation field, especially motivated by the BeiDou Program. In this paper, the current status, technologies and developments in satellite positioning and navigation in China are introduced. Firstly, an overview and update of the BeiDou Program is presented, known as the three-step development strategy for different services. Then signal design for the BeiDou system is discussed, including the generation of pseudo-random noise (PRN) codes for currently available signal B1, and the investigation of a new signal modulation scheme for interoperability at open frequency B1C. The B1C signal should comply to Multiplexed Binary Offset Carrier (MBOC) constrains, and a modulation called Quadrature Multiplexed BOC (QMBOC) is presented, which is equivalent to time-multiplexed BOC (TMBOC) for GPS and composite BOC (CBOC) for Galileo, while overcomes the drawback of CBOC. Besides, the inter and intra system compatibility is discussed, based on the effective C/N0 proposed by International Telecommunication Union (ITU). After that, receiver technologies in challenging environments are introduced, such as weak signal acquisition and assisted GNSS (A-GNSS). Moreover, a method of ambiguity mitigation for adaptive digital beam forming (ADBF) in large spacing antenna arrays is proposed, by which interference suppression is available. Furthermore, cutting edge technologies are brought in, including seamless navigation for indoor and outdoor, and collaborative navigation. After all, GNSS applications in China for industry and daily life are shown, as well as the market prospection.

In the framework of the modernization plan of COMPASS system, the existing COMPASS signals should be transmitted along with the modernized signals to maintain backward compatibility. In this paper, an efficient multiplexing scheme based on the optimal aligning method for combining COMPASS Phase II B3 and Phase III B3 signals is proposed, which offers significantly higher efficiency than Interplex and Generalized Majority Voting (GMV) multiplexing methods. The proposed scheme can provide potential opportunities for COMPASS system and other global navigation satellite systems (GNSS) modernization and construction plans.

The even-shift orthogonal sequence whose out-of-phase aperiodic autocorrelation function takes zero at any even shifts is generalized to multi-dimension called even-shift orthogonal array (E-array), and the logic function of E-array of power-of-two length is clarified. It is shown that E-array can be constructed by complementary arrays, which mean pairs of arrays that the sum of each aperiodic autocorrelation function at the same phase shifts takes zero at any shift except zero shift, as well as the one-dimensional case. It is also shown that the number of mates of E-array with which the cross correlation function between E-arrays takes zero at any even shifts is equal to the dimension. Furthermore it is investigated that E-array possesses good aperiodic autocorrelation that the rate of zero correlation values to array length approaches one as the dimension becomes large.

Establishing peer-to-peer (P2P) live streaming for mobile ad hoc network (MANET) requires an efficient scheme to deliver the real-time data in the infrastructure-less disaster environment. However, P2P membership management is difficult in the dynamic mobility and resource limited MANET. In this paper, we present a cross-layer design for P2P-MANET which integrates P2P DHT-based routing protocol and IPv6 routing protocol. Therefore, the proposed scheme can manage and recover the P2P overlay as well as selecting efficient routing path to multicast video streaming. The simulation results demonstrate that the proposed scheme performs relatively better than the layered approach or the off-the-shelf design in terms of the playback continuity and signaling overhead.

In the infrastructure-less disaster environment, the application of the peer-to-peer (P2P) group conference over mobile ad hoc network (MANET) can be used to communicate with each other when the rescue crews search the survivors but work separately. However, there still are several problems of in-time multimedia delivery in P2P-MANET: (1) MANET mobility influences the maintenance of P2P overlay. (2) P2P overlay is not proximal to MANET topology, this leads to the inefficient streaming delivery. (3) The unreliable wireless connection leads to the difficulty of multi-source P2P group conferencing. Therefore, P2P conferencing cannot work well on MANET. To overcome the above disadvantages, in this paper, we present a cross-layer P2P group conferencing mechanism over MANET, called RING (Real-time Intercommunication Network Gossip). The RING uses the ring overlay to manage peers and utilizes the cross-layer mechanism to force the ring overlay to be proximal to MANET topology. Therefore, RING can lead efficient in-time multimedia streaming delivery. On the other hand, the ring overlay can deal with peer joining/leaving fast and simply, and improves the delivery efficiency with the minimum signaling overhead. Through mathematical theory and a series of experiments, we demonstrate that RING is workable and it can shorten the source-to-end delay with minimal signaling overhead.

This paper presents a response time acceleration technique in a high-gain capacitive-feedback frontend amplifier (FA) for high output impedance sensors. Using an auxiliary amplifier as a unity-gain buffer, a sample-and-hold capacitor which is used for band-limiting and sampling the FA output is driven at the beginning of the transient response to make the response faster and then it is re-charged directly by the FA output. A condition and parameters for the response time acceleration using this technique while maintaining the noise level unaffected are discussed. Theoretical analysis and simulation results show that the response time can be less than half of the case without the acceleration technique for the specified settling error of less than 0.5%.

We propose a methodology of loop design optimization for fourth-order fractional-N phase locked loop (PLL) frequency synthesizers featuring a short settling time of 5 µsec for applications in an active RFID (radio frequency identification) and automobile smart-key systems. To establish the optimized design flow, equations presenting the relationship between the specification and PLL loop parameters in terms of settling time, loop bandwidth, phase margin, and phase noise are summarized. The proposed design flow overcomes the settling time inaccuracy in conventional second-order approximation methods by obtaining the accurate relationship between settling time and loop bandwidth with the MATLAB Control System Toolbox for the fourth-order PLLs. The proposed flow also features the worst-case design by taking account of the process, voltage, and temperature (PVT) variations in loop filter components, and considers the tradeoff between phase noise and area. The three-step optimization process consists of 1) the derivation of the accurate relationship between the settling time and loop bandwidth for various PVT conditions, 2) the derivation of phase noise and area as functions of area-dominant filter capacitance, and 3) the derivation of all PLL loop components values. The optimized design result is compared with circuit simulations using an actually designed fourth-order fractional-N PLL in a 1.8 V 0.18 µm CMOS technology. The error between the design and simulation for the setting time is reduced from 0.63 µsec in the second-order approximation to 0.23 µsec in the fourth-order optimization that proves the validity of the proposed method for the high-speed settling operations.

In this letter, we provide an asymptotic error rate performance evaluation of space-time block codes from coordinate interleaved orthogonal designs (STBCs-CIODs), especially in shadowed Rayleigh fading channels. By evaluating a simplified probability density function (PDF) of Rayleigh and Rayleigh-lognormal channels affecting the STBC-CIOD system, we derive an accurate closed-form approximation for the tight upper and lower bounds on the symbol error rate (SER). We show that shadowing asymptotically affects coding gain only, and conclude that an increase in diversity order under shadowing causes slower convergence to asymptotic bound due to the relatively larger loss of coding gain. By comparing the derived formulas and Monte-Carlo simulations, we validate the accuracy of the theoretical results.

Ternary content addressable memory (TCAM) is becoming very popular for designing high-throughput forwarding engines on routers. However, TCAM has potential problems in terms of hardware and power costs, which limits its ability to deploy large amounts of capacity in IP routers. In this paper, we propose new hardware architecture for fast forwarding engines, called fast prefix search RAM-based hardware (FPS-RAM). We designed FPS-RAM hardware with the intent of maintaining the same search performance and physical user interface as TCAM because our objective is to replace the TCAM in the market. Our RAM-based hardware architecture is completely different from that of TCAM and has dramatically reduced the costs and power consumption to 62% and 52%, respectively. We implemented FPS-RAM on an FPGA to examine its lookup operation.

This paper presents a tutorial overview of Continuous-Time Delta-Sigma Modulators (CTDSM); their operating principles to understand what is important intuitively and architectures to achieve higher conversion efficiency and to operate low supply voltage, design methods against loop stability problem, tuning methods of the bandwidth and so on. A survey of cutting-edge CMOS implementations is described.

It is shown that it is feasible to apply 0.5-V 6-T SRAM cells in a 25-nm high-speed 1-Gb e-SRAM. In particular, for coping with rapidly reduced voltage margin as VDD is reduced, a boosted word-voltage scheme is first proposed. Second, Vt variations are reduced with repair techniques and nanoscale FD-MOSFETs to further widen the voltage margin. Third, a worst case design is developed, for the first time, to evaluate the cell. This design features a dynamic margin analysis and takes subthreshold current, temperature, and Vt variations and their combination in the cell into account. Fourth, the proposed scheme is evaluated by applying the worst-case design and a 25-nm planar FD-SOI MOSFET. It is consequently found that the scheme provides a wide margin and high speed even at 0.5 V. A 0.5-V high-speed 25-nm 1-Gb SRAM is thus feasible. Finally, to further improve the scheme, it is shown that it is necessary to use FinFETs and suppress and compensate process, voltage, and temperature variations in a chip and wafer.

In a large queuing system, the effect of the ratio of the filled data on the queue and waiting time from the head of a queue to the service gate are important factors for process efficiency because they are too large to ignore. However, many research works assumed that the factors can be considered to be negligible according to the queuing theory. Thus, the existing queuing models are not applicable to the design of large-scale systems. Such a system could be used as a product classification center for a home delivery service. In this paper, we propose a tree-queue model for large-scale systems that is more adaptive to efficient processes compared to existing models. We analyze and design a mean waiting time equation related to the ratio of the filled data in the queue. Based on simulations, the proposed model demonstrated improvement in process-efficiency, and it is more suitable to realistic system modeling than other compared models for large-scale systems.

We propose a C-testable multiple-block carry select adder with respect to the cell fault model. Full adders and 2:1 multiplexers are considered as cells. By an additional external input, we obtain a C-testable carry select adder. We only modify the least significant position of each block. The adder is testable with a test set consisting of 16 patterns regardless of the size of each block and the number of blocks. This is the minimum test set for the adder. We show two gate-level implementations of the adder which are testable with a test set of 9 patterns and 7 patterns respectively, with respect to the single stuck-at fault model.

Hybrid wired/wireless on-chip network is a promising communication architecture for multi-/many-core SoC. For application-specific SoC design, it is important to design a dedicated on-chip network architecture according to the application-specific nature. In this paper, we propose a heuristic wireless link allocation algorithm for creating hybrid on-chip network architecture. The algorithm can eliminate the performance bottleneck by replacing multi-hop wired paths by high-bandwidth single-hop long-range wireless links. The simulation results show that the hybrid on-chip network designed by our algorithm improves the performance in terms of both communication delay and energy consumption significantly.

This letter proposes an algorithm of determining the BER-minimized block delay for detection and the associated precoder design once the channel state information and limited transmission power are given. Simulation cases demonstrate the adjusting capability of the proposed algorithm for achieving best BER performance of the joint linear transceiver design.

Partially parallel decoding architectures are widely used in the design of low-density parity-check (LDPC) decoders, especially for quasi-cyclic (QC) LDPC codes. To comply with the code structure of parity-check matrices of QC-LDPC codes, many small memory blocks are conventionally employed in this architecture. The total memory area usually dominates the area requirement of LDPC decoders. This paper proposes a low-complexity memory access architecture that merges small memory blocks into memory groups to relax the effect of peripherals in small memory blocks. A simple but efficient algorithm is also presented to handle the additional delay elements introduced in the memory merging method. Experiment results on a rate-1/2 parity-check matrix defined in the IEEE 802.16e standard show that the LDPC decoder designed using the proposed memory access architecture has the lowest area complexity among related studies. Compared to a design with the same specifications, the decoder implemented using the proposed architecture requires 33% fewer gates and is more power-efficient. The proposed new memory access architecture is thus suitable for the design of low-complexity LDPC decoders.

In this paper, we propose a placement and routing method for a new memory-based programmable logic device (MPLD) and confirm its capability by placing and routing benchmark circuits. An MPLD consists of multiple-output look-up tables (MLUTs) that can be used as logic and/or routing elements, whereas field programmable gate arrays (FPGAs) consist of LUTs (logic elements) and switch blocks (routing elements). MPLDs contain logic circuits more efficiently than FPGAs because of their flexibility and area efficiency. However, directly applying the existing placement and routing algorithms of FPGAs to MPLDs overcrowds the placed logic cells and causes a shortage of routing domains between logic cells. Our simulated annealing-based method considers the detailed wire congestion and nearness between logic cells based on the cost function and reserves the area for routing. In the experiments, our method reduced wire congestion and successfully placed and routed 27 out of 31 circuits, 13 of which could not be placed or routed using the versatile place and route tool (VPR), a well-known method for FPGAs.

Conventional algorithms for the joint estimation of carrier frequency offset (CFO) and I/Q imbalance no longer work when the I/Q imbalance depends on the frequency. In order to correct the imbalance across many frequencies, the compensator needed is a filter as opposed to a simple gain and phase compensator. Although, algorithms for estimating the optimal coefficients of this filter exist, their complexity is too high for hardware implementation. In this paper we present a new low complexity algorithm for joint estimation of CFO and frequency dependent I/Q imbalance. For the first part, we derive the estimation scheme using the linear least squares algorithm and examine its floating point performance compared to conventional algorithms. We show that the proposed algorithm can completely eliminate BER floor caused by CFO and I/Q imbalance at a lesser complexity compared to conventional algorithms. For the second part, we examine the hardware complexity in fixed point hardware and latency of the proposed algorithm. Based on BER performance, the circuit needs a wordlength of at least 16 bits in order to properly estimate CFO and I/Q imbalance. In this configuration, the circuit is able to achieve a maximum speed of 115.9 MHz in a Virtex 5 FPGA.

An FPGA plays an essential role in industrial products due to its fast, stable and flexible features. But the power consumption of FPGAs used in portable devices is one of critical issues. Top-down hierarchical design method is commonly used in both ASIC and FPGA design. But, in the case where plural modules are integrated in an FPGA and some of them might be in sleep-mode, current FPGA architecture cannot be fully effective. In this paper, coarse-grained power gating FPGA architecture is proposed where a whole area of an FPGA is partitioned into several regions and power supply is controlled for each region, so that modules in sleep mode can be effectively power-off. We also propose a region oriented FPGA placement algorithm fitted to this user's hierarchical design based on VPR [1]. Simulation results show that this proposed method could reduce power consumption of FPGA by 38% on average by setting unused modules or regions in sleep mode.