A C-testable 4-2 adder tree for an easily testable high-speed multiplier is proposed, and a recursive method for test generation is shown. By using the specific patterns that we call 'alternately inverted patterns,' the adder tree, as well as partial product generators, can be tested with 14 patterns regardless of its operand size under the cell fault model. The test patterns are easily fed through the partial product generators. The hardware overhead of the 4-2 adder tree with partial product generators for a 64-bit multiplier is about 15%. By using a previously proposed easily testable adder as the final adder, we can obtain an easily testable high-speed multiplier.

Design of high gain and high efficiency antennas is one of the key challenges in antenna engineering and especially in millimeter wave communication systems. Various types of planar waveguide arrays with series-fed traveling wave operation have been developed in Tokyo Tech with the special focus upon efficiency enhancement as well as reduction of fabrication cost. In this review, four kinds of single layer waveguide arrays characterized with the series fed travelling wave operation are surveyed first. To cope with the bandwidth narrowing effects due to long line effects associated with the series fed operation, authors have introduced partially corporate feed embedded in the single layer waveguide. They further extended the study to cover fully corporate feed arrays with multiple layer waveguide as well; a new fabrication technique of diffusion bonding of laminated thin plates has the potential to realize the low cost mass production of multi-layer structures for the millimeter wave application. Secondly, the novel methods for loss evaluation of copper plate substrate are established for the design of post-wall waveguide arrays where dielectric loss and conductor loss is determined in wide range of millimeter wave band, by using the Whispering gallery mode resonator. This enables us to design the planar arrays with the loss taken into account. Finally, the planar arrays are now applied to two kinds of systems in the Tokyo Tech millimeter wave project; the indoor short range file-transfer systems and the outdoor communication systems for the medium range backhaul links. The latter has been field-tested in the model network built in Tokyo Tech Ookayama campus. Early stage progress of the project including unique propagation data is also reported.

This paper focuses on the problem of performance degradation in mismatched speech recognition. The F-Ratio analysis method is utilized to analyze the significance of different frequency bands for speech unit classification, and we find that frequencies around 1 kHz and 3 kHz, which are the upper bounds of the first and the second formants for most of the vowels, should be emphasized in comparison to the Mel-frequency cepstral coefficients (MFCC). The analysis result is further observed to be stable in several typical mismatched situations. Similar to the Mel-Frequency scale, another frequency scale called the F-Ratio-scale is thus proposed to optimize the filter bank design for the MFCC features, and make each subband contains equal significance for speech unit classification. Under comparable conditions, with the modified features we get a relative 43.20% decrease compared with the MFCC in sentence error rate for the emotion affected speech recognition, 35.54%, 23.03% for the noisy speech recognition at 15 dB and 0 dB SNR (signal to noise ratio) respectively, and 64.50% for the three years' 863 test data. The application of the F-Ratio analysis on the clean training set of the Aurora2 database demonstrates its robustness over languages, texts and sampling rates.

This paper presents a low-power System on Chip (SOC) architecture for the v2.0+EDR (Enhanced Data Rate) Bluetooth and its applications. Our design includes a link controller, modem, RF transceiver, Sub-Band Codec (SBC), Expanded Instruction Set Computer (ESIC) processor, and peripherals. To decrease power consumption of the proposed SOC, we reduce data transfer using a dual-port memory, including a power management unit, and a clock gated approach. We also address some of issues and benefits of reusable and unified environment on a centralized data structure and SOC verification platform. This includes flexibility in meeting the final requirements using technology-independent tools wherever possible in various processes and for projects. The other aims of this work are to minimize design efforts by avoiding the same work done twice by different people and to reuse the similar environment and platform for different projects. This chip occupies a die size of 30 mm2 in 0.18 µm CMOS, and the worst-case current of the total chip is 54 mA.

We present a session initiation protocol (SIP) network design for a voice-over-IP network to prevent congestion caused by people calling friends and family after a disaster. The design increases the capacity of SIP servers in a network by using all of the SIP servers equally. It takes advantage of the fact that equipment for voice data packets is different from equipment for signaling packets in SIP networks. Furthermore, the design achieves simple routing on the basis of telephone numbers. We evaluated the performance of our design in preventing congestion through simulation. We showed that the proposed design has roughly 20 times more capacity, which is 57 times the normal load, than the conventional design if a disaster were to occur in Niigata Prefecture struck by the Chuetsu earthquake in 2004.

A novel construction of complementary sequences with multi-width zero cross-correlation zone (ZCCZ) is presented based on the interleaving iteration of a basic kernel set. The presented multi-width ZCCZ complementary (MWZC) sequences can be divided into multiple sequence groups, the correlation functions of which possess one-width intragroup ZCCZ and multi-width intergroup ZCCZ. When an arbitrary orthogonal sequence set with set size equal to sequence length is used as a basic kernel set, the constructed MWZC sequence set and the combination sets of specific subsets with each subset including several groups can be optimal with respect to the theoretical bound on set size. In addition, the MWZC sequence set includes complementary sequence sets with one-width or two-width ZCCZ as special subsets, and allows a more flexible choice of sequence parameters.

The design of microstrip bandpass filters using stepped-impedance resonators (SIRs) is examined. The passband center frequency for the WCDMA-FDD (uplink band) Japanese cellular system is 1950 MHz with a 60-MHz bandwidth. The SIR physical characteristic can be designed using a SIR characteristic chart based on second harmonic suppression. In our filter design, passband design charts were obtained through the design procedure. Tchebycheff and maximally flat bandpass filters of any bandwidth and any number of steps can be designed using these passband design charts. In addition, sharp skirt characteristics in the passband can be realized by having two transmission zeros at both adjacent frequency bands by using open-ended quarter-wavelength stubs at input and output ports. A new even-mode harmonics suppression technique is proposed to enable a wide rejection band having a high suppression level. The unloaded quality factor of the resonator used in the proposed filters is greater than 240.

This paper deals with a design problem of an observer-based robust stabilizing controller for a class of polytopic uncertain systems. The proposed controller synthesis differs from the conventional quadratic stabilization based on Lyapunov criterion and is based on the computation of the system's trajectory. In this paper, we show a LMI-based design method of the observer-based robust controller. The effectiveness of the proposed controller design approach is presented through a simple numerical example.

We present a graph model and an ILP model for TAM design for transparency-based SoC testing. The proposed method is an extension of a previous work proposed by Chakrabarty with respect to the following three points: (1) constraint relaxation by considering test data flow for each core separately, (2) optimization of the cost for transparency as well as the cost for additional interconnect area simultaneously and (3) consideration of additional bypass paths. Therefore, the proposed ILP model can represent various problems including the same problem as the previous work and produce better results. Experimental results show the effectiveness and flexibility of the proposed method compared to the previous work.

In digital signal processing, the sampling theorem states that any real valued function f can be reconstructed from a sequence of values of f that are discretely sampled with a frequency at least twice as high as the maximum frequency of the spectrum of f. This theorem can also be applied to functions over finite domain. Then, the range of frequencies of f can be expressed in more detail by using a bounded set instead of the maximum frequency. A function whose range of frequencies is confined to a bounded set is referred to as bandlimited function. And a sampling theorem for bandlimited functions over Boolean domain has been obtained. Here, it is important to obtain a sampling theorem for bandlimited functions not only over Boolean domain (GF(2)n domain) but also over GF(q)n domain, where q is a prime power and GF(q) is Galois field of order q. For example, in experimental designs, although the model can be expressed as a linear combination of the Fourier basis functions and the levels of each factor can be represented by GF(q), the number of levels often take a value greater than two. However, the sampling theorem for bandlimited functions over GF(q)n domain has not been obtained. On the other hand, the sampling points are closely related to the codewords of a linear code. However, the relation between the parity check matrix of a linear code and any distinct error vectors has not been obtained, although it is necessary for understanding the meaning of the sampling theorem for bandlimited functions. In this paper, we generalize the sampling theorem for bandlimited functions over Boolean domain to a sampling theorem for bandlimited functions over GF(q)n domain. We also present a theorem for the relation between the parity check matrix of a linear code and any distinct error vectors. Lastly, we clarify the relation between the sampling theorem for functions over GF(q)n domain and linear codes.

This paper discusses recent trends in the area of low-power, high-performance A/D conversion. We examine survey data collected over the past twelve years to show that the conversion energy of ADCs has halved every two years, while the speed-resolution product has doubled approximately only every four years. A closer inspection on the impact of technology scaling, and developments in ADC design are then presented to explain the observed trends. Finally, we review opportunities in digitally assisted design for the most popular converter architectures.

With the big success of 802.11 wireless networks, there have been many proposals addressing end-to-end QoS guarantees in 802.11 WLAN. However, we have found that current end-to-end QoS architectures lack of one or more important properties such as cross-layer interaction, end-to-end integration, reconfigurability and modularity. In this work, we present an end-to-end reference QoS architecture for 802.11 WLAN that encapsulates in an unifying fashion software-based QoS components (mechanisms, algorithms, services), proposed in the literature. To show the usefulness and correctness of the reference architecture, we present three case studies of end-to-end QoS architectures addressing different QoS requirements such as bandwidth and delay with different approaches such as differentiated services and integrated services. We will give an architectural comparison and performance evaluation of these architectures. We believe the reference QoS architectures can help QoS designers to understand the importance and the complexity of various QoS components during the design phase and thus choose these QoS components appropriately.

This paper presents a novel cross-layer approach to explore selection diversity for distributed clustering based wireless sensor networks (WSNs) by selecting a proper cluster-head. We develop and analyze an instantaneous channel state information (CSI) based cluster-head selection algorithm for a distributed, dynamic and randomized clustering based WSN. The proposed cluster-head selection scheme is also random and capable to distribute the energy uses among the nodes in the network. We present an analytical approach to evaluate the energy efficiency and system lifetime of our proposal. Analysis shows that the proposed scheme outperforms the performance of additive white Gaussian noise (AWGN) channel under Rayleigh fading environment. This proposal also outperforms the existing cooperative diversity protocols in terms of system lifetime and implementation complexity.

We demonstrated an automated passive-transmission-line routing tool for single-flux-quantum (SFQ) circuits. The tool is based on the A* algorithm, which is widely used in CMOS LSI design, and tuned for microstrip/strip lines formed in the SRL 4-Nb layer structure. In large-scale SFQ circuits with 10000-20000 Josephson junctions, such as microprocessors, 80-90% of the wires can be automatically routed in about ten minutes. We verified correct operation above 40 GHz for an automatically routed 44 switch circuit from on-chip high-speed tests. The resulting circuit size and operating frequency were comparable to those of a manually designed result. We believe that the tool is useful for large-scale SFQ circuit design using conventional fabrication processes.

Limitations are found in the recent Internet because a lot of functions and protocols are patched to the original suite of layered protocols without considering global optimization. This reveals that end-to-end argument in the original Internet was neither sufficient for the current societal network and nor for a sustainable network of the future. In this position paper, we present design guidelines for a future network, which we call the New Generation Network, which provides the inclusion of diverse human requirements, reliable connection between the real-world and virtual network space, and promotion of social potentiality for human emergence. The guidelines consist of the crystal synthesis, the reality connection, and the sustainable & evolutional guidelines.

This paper presents an ultra-low-power single-chip sensor-node VLSI for wireless-sensor-network applications. A communication centric design approach has been introduced to reduce the power consumption of the RF circuits and the entire sensor network system, through a vertical cooperative design among circuits, architecture, and communication protocols. The sensor-node LSI features a synchronous media access control (MAC) protocol and integrates a transceiver, i8051 microcontroller, and dedicated MAC processor. The test chip occupies 33 mm2 in a 180-nm CMOS process, including 1.38 M transistors. It dissipates 58.0 µW under a network environment.

Proposed in this paper is a low power BIST architecture using the pattern mapping method based on the transition freezing method. The transition freezing method generates frozen patterns dynamically according to the transition tendency of an LFSR. This leads to an average power reduction of 60%. However, the patterns have limitations of 100% fault coverage due to random resistant faults. Therefore, in this paper, those faults are detected by mapping useless patterns among frozen patterns to the patterns generated by an ATPG. Throughout the scheme, 100% fault coverage is achieved. Moreover, we have reduced the amount of applied patterns, the test time, and the power dissipation.

Two essential technologies for a 3D Solid State Drive (3D-SSD) with a boost converter are presented in this paper. The first topic is the spiral inductor design which determines the performance of the boost converter, and the second is the effect of TSV's on the boost converter. These techniques are very important in achieving a 3D-SSD with a boost converter. In the design of the inductor, the on-board inductor from 250 nH to 320 nH is the best design feature that meets all requirements, including high output voltage above 20 V, fast rise time, low energy consumption, and area smaller than 25 mm2. The use of a boost converter with the proposed inductor leads to a reduction of the energy consumption during the write operation of the proposed 1.8-V 3D-SSD by 68% compared with the conventional 3.3-V 3D-SSD with the charge pump. The feasibility of 3D-SSD's with Through Silicon Vias (TSV's) connections is also discussed. In order to maintain the advantages of the boost converter over the charge pump, the reduction of the parasitic resistance of TSV's is very important.

In this paper, a design methodology for the minimization of various performance metrics of MOS Current-Mode Logic (MCML) circuits is described. In particular, it allows to minimize the delay under a given power consumption, the power consumption under a given delay and the power-delay product. Design solutions can be evaluated graphically or by simple and effective automatic procedures implemented within the MATLAB environment. The methodology exploits the novel concepts of crossing-point current and crossing-point capacitance. A useful feature of it is that it provides the designer with useful insights into the dependence of the performance metrics on design variables and fan-out capacitance. The methodology was validated by designing several MCML circuits in an IBM 130 nm CMOS process.

This paper presents a selective scan slice grouping technique for test data compression. In conventional selective encoding methods, the existence of a conflict bit contributes to large encoding data. However, many conflict bits are efficiently removed using the scan slice grouping technique, which leads to a dramatic improvement of encoding efficiency. Experiments performed with large ITC'99 benchmark circuits presents the effectiveness of the proposed technique and the test data volume is reduced up to 92% compared to random-filled test patterns.