The Wireless Sensor Network (WSN) uses autonomous sensor nodes to monitor a field. These sensor nodes sometimes act as relay nodes for each other. In this paper, the performance of the WSN using fixed relay nodes and Multiple-Input Multiple-Output (MIMO) technology necessary for future wireless communication is evaluated in terms of the channel capacity of the MIMO system and the number of sensor nodes served by the system. Accordingly, we propose an optimum topology for the WSN backbone named Connected Relay Node Double Cover (CRNDC), which can recover from a single fault, the algorithms (exhaustive search and other two approximation methods) to find the optimum distance to place the relay nodes from sink node, and the height of the sink and relay nodes to be placed by using the pathloss model. The performances of different MIMO-WSN configurations over conventional WSN are evaluated, and the direct relationship between relay position and minimum required channel capacity are discovered.

This letter deals with the time-domain estimation of time-varying channels in orthogonal frequency-division multiplexing (OFDM) systems. The general complex exponential basis expansion model (GCE-BEM) is used to capture the time variation of the channel within an OFDM block. The design criterion of optimal training for OFDM systems in time-varying channels is derived. This optimal training enables the complete elimination of the interference from data symbols and minimizes the noise effect on channel estimation. The design criterion can be used for both pilot symbol aided modulation (PASM) and superimposed training OFDM systems over time-varying channels.

In this paper, we present an efficient low power scan test technique which simultaneously reduces both average and peak power consumption. The selective scan chain activation scheme removes unnecessary scan chain utilization during the scan shift and capture operations. Statistical scan cell reordering enables efficient scan chain removal. The experimental results demonstrated that the proposed method constantly reduces the average and peak power consumption during scan testing.

Evolvable hardware (EHW) is a new research field about the use of Evolutionary Algorithms (EAs) to construct electronic systems. EHW refers in a narrow sense to use evolutionary mechanisms as the algorithmic drivers for system design, while in a general sense to the capability of the hardware system to develop and to improve itself. Genetic Algorithm (GA) is one of typical EAs. We propose optimal circuit design by using GA with parameterized uniform crossover (GApuc) and with fitness function composed of circuit complexity, power, and signal delay. Parameterized uniform crossover is much more likely to distribute its disruptive trials in an unbiased manner over larger portions of the space, then it has more exploratory power than one and two-point crossover, so we have more chances of finding better solutions. Its effectiveness is shown by experiments. From the results, we can see that the best elite fitness, the average value of fitness of the correct circuits and the number of the correct circuits of GApuc are better than that of GA with one-point crossover or two-point crossover. The best case of optimal circuits generated by GApuc is 10.18% and 6.08% better in evaluating value than that by GA with one-point crossover and two-point crossover, respectively.

This paper presents a novel method using multi-objective optimization algorithm to automatically find the best solution from a topology library of analog circuits. Firstly this method abstracts the Pareto-front of each topology in the library by SPICE simulation. Then, the Pareto-front of the topology library is abstracted from the individual Pareto-fronts of topologies in the library followed by the theorem we proved. The best solution which is defined as the nearest point to specification on the Pareto-front of the topology library is then calculated by the equations derived from collinearity theorem. After the local searching using Nelder-Mead method maps the calculated best solution backs to design variable space, the non-dominated best solution is obtained. Comparing to the traditional optimization methods using single-objective optimization algorithms, this work can efficiently find the best non-dominated solution from multiple topologies for different specifications without additional time-consuming optimizing iterations. The experiments demonstrate that this method is feasible and practical in actual analog designs especially for uncertain or variant multi-dimensional specifications.

There is a trend towards flexible radios which are able to cope with a range of wireless communication standards. For the integrated processing of widely different signals -- including single-carrier, multi-carrier, and spread-spectrum signals -- monolithic baseband receivers need universal formats for the signal representation and channel description. We consider a reconfigurable receiver architecture building on concepts from time-frequency (TF) signal analysis. The core elements are TF signal representations in form of a Gabor expansion along with a compatible parameterization of time-variant channels. While applicable to arbitrary signal types, the TF channel parameterization offers similar advantages as the frequency domain channel description employed by orthogonal frequency-division multiplexing receivers. The freedom in the choice of the underlying analysis window function and the scalability in time and frequency facilitate the handling of diverse signal types as well as the adaptation to radio channels with different delay and Doppler spreads. Optimized window shapes limit the inherent model error, as demonstrated using the example of direct-sequence spread-spectrum signaling.

The researches on predicting and removing of lithographic hot-spots have been prevalent in recent semiconductor industries, and known to be one of the most difficult challenges to achieve high quality detection coverage. To provide physical design implementation with designer's favors on fixing hot-spots, in this paper, we present a noble and accurate hot-spot detection method, so-called "leveling and scoring" algorithm based on weighted combination of image quality parameters (i.e., normalized image log-slope (NILS), mask error enhancement factor (MEEF), and depth of focus (DOF)) from lithography simulation. In our algorithm, firstly, hot-spot scoring function considering severity level is calibrated with process window qualification, and then least-square regression method is used to calibrate weighting coefficients for each image quality parameter. In this way, after we obtain the scoring function with wafer results, our method can be applied to future designs of using the same process. Using this calibrated scoring function, we can successfully generate fixing guidance and rule to detect hot-spot area by locating edge bias value which leads to a hot-spot-free score level. Finally, we integrate the hot-spot fixing guidance information into layout editor to facilitate the user-favorable design environment. Applying our method to memory devices of 60 nm node and below, we could successfully attain sufficient process window margin to yield high mass production.

Recently, two-level cache, L1 cache and L2 cache, is commonly used in a processor. Particularly in an embedded system whereby a single application or a class of applications is repeatedly executed on a processor, its cache configuration can be customized such that an optimal one is achieved. An optimal two-level cache configuration can be obtained which minimizes overall memory access time or memory energy consumption by varying the three cache parameters: the number of sets, a line size, and an associativity, for L1 cache and L2 cache. In this paper, we first extend the L1 cache simulation algorithm so that we can explore two-level cache configuration. Second, we propose two-level cache design space exploration algorithms: CRCB-T1 and CRCB-T2, each of which is based on applying Cache Inclusion Property to two-level cache configuration. Each of the proposed algorithms realizes exact cache simulation but decreases the number of cache hit/miss judgments by a factor of several thousands. Experimental results show that, by using our approach, the number of cache hit/miss judgments required to optimize a cache configurations is reduced to 1/50-1/5500 compared to the exhaustive approach. As a result, our proposed approach totally runs an average of 1398.25 times faster compared to the exhaustive approach. Our proposed cache simulation approach achieves the world fastest two-level cache design space exploration.

Multitude parameters in the design process of a reconfigurable instruction-set processor (RISP) may lead to a large design space and remarkable complexity. Quantitative design approach uses the data collected from applications to satisfy design constraints and optimize the design goals while considering the applications' characteristics; however it highly depends on designer observations and analyses. Exploring design space can be considered as an effective technique to find a proper balance among various design parameters. Indeed, this approach would be computationally expensive when the performance evaluation of the design points is accomplished based on the synthesis-and-simulation technique. A combined analytical and simulation-based model (CAnSO**) is proposed and validated for performance evaluation of a typical RISP. The proposed model consists of an analytical core that incorporates statistics collected from cycle-accurate simulation to make a reasonable evaluation and provide a valuable insight. CAnSO has clear speed advantages and therefore it can be used for easing a cumbersome design space exploration of a reconfigurable RISP processor and quick performance evaluation of slightly modified architectures.

3D graphics application is widely used in consumer electronics which is an inevitable tendency in the future. In general, the higher abstraction level is used to model a complex system like 3D graphics SoC. However, the concerned issue is that how to use efficient methods to traverse design space hierarchically, reduce simulation time, and refine the performance fast. This paper demonstrates a system-level design space exploration model for a tile-based 3D graphics SoC refinement. This model uses UML tools which can assist designers to traverse the whole system and reduces simulation time dramatically by adopting SystemC. As a result, the system performance is improved 198% at geometry function and 69% at rendering function, respectively.

In recent VLSI systems, signal propagation delays are requested to achieve the specifications with very high accuracy. In order to meet the specifications, the routing of a net often needs to be detoured in order to increase the routing delay. A routing method should utilize a routing area with obstacles as much as possible in order to realize the specifications of nets simultaneously. In this paper, a fast longer path algorithm that generates a path of a net in routing grid so that the length is increased as much as possible is proposed. In the proposed algorithm, an upper bound for the length in which the structure of a routing area is taken into account is used. Experiments show that our algorithm utilizes a routing area with obstacles efficiently.

Partial forwarding is a design method to place forwarding paths on a part of processor pipeline. Hardware cost of processor can be reduced without performance loss by partial forwarding. However, compiler with the instruction scheduler which considers partial forwarding structure of the target processor is required since conventional scheduling algorithm cannot make the most of partial forwarding structure. In this paper, we propose a heuristic instruction scheduling method for processors with partial forwarding structure. The proposed algorithm uses available distance to schedule instructions which are suitable for the target partial forwarding processor. Experimental results show that the proposed method generates near-optimal solutions in practical time and some of the optimized codes for partial forwarding processor run in the shortest time among the target processors. It also shows that the proposed method is superior to hazard detection unit.

This paper presents a gate-block selection algorithm, which can synthesize a proper parameter extractor of the pre-computation-based content-addressable memory (PB-CAM) to enhance power efficiency for specific applications such as embedded systems, microprocessor and SOC, etc. Furthermore, a novel CAM cell design with single bit-line is proposed. The proposed CAM cell design requires only one heavy loading bit-line and merely is constructed with eight transistors. The whole PB-CAM design was described in Spice with TSMC 0.35 µm double-poly quadruple-metal CMOS process. We used Synopsys Nanosim to estimate power consumption. With a 128 words by 32 bits CAM size, the experimental results showed that our proposed PB-CAM effectively reduces 18.21% of comparison operations in the CAM and saves 16.75% in power reduction by synthesizing a proper parameter extractor of the PB-CAM compared with the 1's count PB-CAM. This implies that our proposed PB-CAM is more flexible and adaptive for specific applications.

In modern VLSI physical design, huge integration scale necessitates hierarchical design and IP reuse to cope with design complexity. Besides, interconnect delay becomes dominant to overall circuit performance. These critical factors require some modules to be placed along designated boundaries to effectively facilitate hierarchical design and interconnection optimization related problems. In this paper, boundary constraints of general floorplan are solved smoothly based on the novel representation Single-Sequence (SS). Necessary and sufficient conditions of rooms along specified boundaries of a floorplan are proposed and proved. By assigning constrained modules to proper boundary rooms, our proposed algorithm always guarantees a feasible SS code with appropriate boundary constraints in each perturbation. Time complexity of the proposed algorithm is O(n). Experimental results on MCNC benchmarks show effectiveness and efficiency of the proposed method.

This paper proposes an Integer Linear Programming (ILP)-based power minimization method by partitioning into regions, first, with three different VDD's(PM3V), and, secondly, with two different VDD's(PM2V). To reduce the solving time of triple-VDD case (PM3V), we also proposed a partitioned ILP method(p-PM3V). The proposed method provides 29% power saving on the average in the case of triple-VDD compared to the case of single VDD. Power reduction of PM3V compared to Clustered Voltage Scaling (CVS) was about 18%. Compared to the unpartitioned ILP formulation(PM3V), the partitioned ILP method(p-PM3V) reduced the total solution time by 46% at the cost of additional power consumption within 1.3%.

The distributed antenna system (DAS) offers significant power savings but only if the antennas are properly located. In this letter, we convert antenna location optimization to the codebook design problem. For the widely studied circular-layout DAS with uniform user distribution, we derive closed-form expressions for antenna locations that yield near-optimal performance. For more general user distribution and antenna topology, the codebook design algorithms can provide numerical optimization results with acceptable performance and low complexity.

This letter proposes a type of mutually cooperative relaying (MCR) scheme based on a spatially coordinate-interleaved orthogonal design (SCID), in which two cooperative users are spatially multiplexed without bandwidth expansion. It provides not only diversity gain (with order of two) as in the existing MCR scheme, but also additional coding gain. Our simulation results demonstrate that the proposed SCID scheme is useful for improving the uplink performance as long as one user can find another active user as a close neighbor that is simultaneously communicating with the same destination, e.g., a base station in the cellular network.

It has been proved that wireless network coding can increase the throughput of multi-access system [2] and bi-directional system [5] by taking the advantage of the broadcast nature of electromagnetic waves. In this paper, we introduce the wireless network coding to cooperative multicast system. We establish a basic 2-source and 2-destination cooperative system model with arbitrary number of relays (2-N-2 system). Then two regenerative network coding (RNC) protocols are designed to execute the basic idea of network coding in complex field (RCNC) and Galois field (RGNC) respectively. We illuminate how network coding can enhance the throughput distinctly in cooperative multicast system. Power allocation schemes as well as precoder design are also carefully studied to improve the system performance in terms of system frame error probability (SFEP).

In this letter, we propose a network-adaptive video streaming scheme based on cross-layered hop-by-hop video rate control in wireless multi-hop networks. We argue that existing end-to-end network-adaptive video rate control schemes, which utilize end-to-end statistics, exhibit serious performance degradation in severely interfered wireless network condition. To cope with this problem, in the proposed scheme, intermediate wireless nodes adjust video sending rate depending upon wireless channel condition measured at MAC (Medium Access Control) layer. Extensive experimental results from an IEEE 802.11a-based testbed show that the proposed scheme improves the perceptual video quality compared to an end-to-end scheme.

This paper presents a grouped scan slice encoding technique using scan slice repetition to simultaneously reduce test data volume and test application time. Using this method, many scan slices that would be incompatible with the conventional selective scan slice method can be encoded as compatible scan slices. Experiments were performed with ISCAS'89 and ITC'99 benchmark circuits, and results show the effectiveness of the proposed method.