This paper presents an automated design of analog circuits starting with idealized elements. Our system first synthesizes circuits using idealized elements by a genetic algorithm (GA). GA evolves circuit topologies and transconductances of idealized elements to achieve the given specifications. The use of idealized elements effectively reduces search space and make the synthesis efficient. Second, idealized elements in a generated circuit are replaced by MOSFETs. Through the two processes, a circuit satisfying the given specifications can be obtained. The capability of this method was demonstrated through experiments of synthesis of a trans-impedance amplifier and a cubing circuit and benchmark tests. The results of the benchmark tests show the proposed CAD is more than 10 times faster than the CAD which does not use idealized elements.

Binary sequences with two-level periodic autocorrelation correspond directly to cyclic (v, k, λ)-designs. When v = 4t-1, k = 2t -1 and λ = t-1, for some positive integer t, the sequence (or design) is called a cyclic Hadamard sequence (or design). For all known examples, v is either a prime number, a product of twin primes, or one less than a power of 2. Except when v = 2k-1, all known examples are based on quadratic residues (using the Legendre symbol when v is prime, and the Jacobi symbol when v = p(p+2) where both p and p+2 are prime); or sextic residues (when v is a prime of the form 4a2 + 27). However, when v = 2k-1, many constructions are now known, including m-sequences (corresponding to Singer difference sets), quadratic and sextic residue sequences (when 2k-1 is prime), GMW sequences and their generalizations (when k is composite), certain term-by-term sums of three and of five m-sequences and more general sums of trace terms, several constructions based on hyper-ovals in finite geometries (found by Segre, by Glynn, and by Maschietti), and the result of performing the Welch-Gong transformation on some of the foregoing.

This paper presents two kinds of new ZCZ codes consisting of trios of two binary sequences and a bi-phase sequence, which can reach the upper bound on the ZCZ codes. From the viewpoint of sequence design, it is shown that they can provide the most effective ASK-CDMA system, which can remove co-channel interference.

Some signal design methods for the approximately synchronized CDMA systems based on complete complementary codes have been proposed. It has been shown that estimating the multipath channels and applying the convolution of the spread signals can increase both the information transmission rate and frequency usage efficiency. There are some variations of such signal design methods using complete complementary codes. The efficiency of the communication systems and information transmission rate depend upon the applied signal design method and the modulation scheme. In this paper, we consider two of these signal design methods. We analyze the bit error rate (BER) performances for both methods through some numerical simulations under the single cell scenario. Numerical results show the BER properties under some modulation schemes such as BPSK, QPSK and 16QAM. Some discussions on the relation between the BER performance and the information transmission rate are also included.

This paper presents constructions of two kinds of sets of sequences with a zero correlation zone, called ZCZ code, which can reach the upper bound of the member size of the sequence set. One is a ZCZ code which can be constructed by a unitary matrix and a perfect sequence. Especially, a ternary perfect sequence with elements 1 and zero can be used to construct the proposed ZCZ code. The other is a ZCZ code of pairs of ternary sequences and binary sequences which can be constructed by an orthogonal matrix that includes a Hadamard matrix and an orthogonal sequence pair. As a special case, an orthogonal sequence pair, which consists of a ternary sequence and a binary sequence, can be used to construct the proposed ZCZ code. These codes can provide CDMA systems without co-channel interference.

To increase the yield of data processing circuits such as adders and logic operation circuits, the bit-slice reconfiguration design has been proposed as an efficient redundant technology for defect-tolerance. Wallace multipliers are a well-known class of high-speed parallel multipliers. Unfortunately, the bit-slice reconfiguration design is not applicable to Wallace multipliers because Wallace multipliers do not have regular bit-slice structure. Therefore, redundant designs for Wallace multipliers have been regarded impossible. This paper proposes a redundant design for Wallace multipliers. In order to design redundant Wallace multipliers, first, 2n heterogeneous slices are considered in a non-redundant nn Wallace multiplier. The proposed redundant Wallace multipliers contain reconfigurable slices which can play the role of both i-th and (i+1)-th slices. Since the i-th slice has a similar structure to the (i+1)-th slice, the reconfigurable slice is not much larger than the i-th slice. This paper also shows a repair procedure for the proposed design. This paper evaluates the proposed design from the viewpoint of the yield, area, effective yield and delay time. For example, the yield of a 3232 Wallace multiplier increases from 0.30 to 0.41 by applying the proposed design while the area increases by a factor of 1.21.

We discuss a new design methodology of polynomial neural networks (PNN) in the framework of genetic algorithm (GA). The PNN is based on the ideas of group method of data handling (GMDH). Each node in the network is very flexible and can carry out polynomial type mapping between input and output variables. But the performances of PNN depend strongly on the number of input variables available to the model, the number of input variables, and the type (order) of the polynomials to each node. In this paper, GA is implemented to better use the optimal inputs and the order of polynomial in each node of PNN. The appropriate inputs and order are evolved accordingly and are tuned gradually throughout the GA iterations. We employ a binary coding for encoding key factors of the PNN into the chromosomes. The chromosomes are made of three sub-chromosomes which represent the order, number of inputs, and input candidates for modeling. To construct model by using significant approximation and generalization, we introduce the fitness function with a weighting factor. Comparisons with other modeling methods and conventional PNN show that the proposed design method offers encouraging advantages and better performance.

The optical network represents a promising approach to achieve a scalable backbone network. In backbone networks, survivability is important because high volumes of traffic are prone to be damaged by faulty equipment. Various design methods for survivable optical networks have been proposed, although none considering the simultaneous maintenance of multiple transmission lines has been proposed to our knowledge. This paper proposes a design method for survivable optical networks where multiple transmission lines sharing common transmission equipment may suffer simultaneous damage, due to failure in the transmission equipment. Moreover, two transmission lines can be maintained simultaneously. A mathematical programming model to obtain the optimum lightpath arrangement is presented assuming three kinds of lightpath recovery schemes. The relation between the required transmission line capacity and the combination pattern of two transmission lines that undergo maintenance is clarified using the proposed design method.

In modern CMOS digital design, the noise immunity has come to have an almost equal importance to the power consumption. In the last decade, many low power design schemes have been presented. However, no one can simply judge which one is the best from the noise immunity point of view. In this paper, we investigate the noise immunity of the static CMOS low power design schemes in terms of logic and delay errors caused by different kinds of noise existing in the static CMOS digital circuits. To fulfill the aims of the paper, first a model representing the different sources of noise in deep submicron design is presented. Then the model is applied to the most famous low power design schemes to find out the most robust one with regard to noise. Our results show the advantages of the dual threshold voltage scheme over other schemes from the noise immunity point of view. Moreover, it indicates that noise should be carefully taken into account when designing low power circuits; otherwise circuit performance would be unexpected. The study is carried out on three circuits; each is designed in five different schemes. The analysis is done using HSPICE, assuming 0.18 µm CMOS technology.

In the optimum design of contactors, it is important to analyze the dynamic behaviors. In this paper, it proposes a new computational approach for analyzing dynamic characteristic of the energy-saving and bouncing-reducing double-coil contactor. According to the contactor's unique characteristic that it has two transferable coils, the paper builds two different sets of equations. One describes the period before the transfer position, and the other describes the period after the transfer position. The equations deal with the electrical circuit, electromagnetic field that can be calculated by using 3-D finite element method and mechanical system considering the influence of friction. The validity of the proposed method is confirmed by experiment. Finally, the paper gives an optimum design for the transfer position of the two coils. The result of the optimum design reduces both of the first and the second bounces of the movable contact.

Developing embedded parallel image processing applications is usually a very hardware-dependent process, often using the single instruction multiple data (SIMD) paradigm, and requiring deep knowledge of the processors used. Furthermore, the application is tailored to a specific hardware platform, and if the chosen hardware does not meet the requirements, it must be rewritten for a new platform. We have proposed the use of design space exploration [9] to find the most suitable hardware platform for a certain application. This requires a hardware-independent program, and we use algorithmic skeletons [5] to achieve this, while exploiting the data parallelism inherent to low-level image processing. However, since different operations run best on different kinds of processors, we need to exploit task parallelism as well. This paper describes how we exploit task parallelism using an asynchronous remote procedure call (RPC) system, optimized for low-memory and sparsely connected systems such as smart cameras. It uses a futures [16]-like model to present a normal imperative C-interface to the user in which the skeleton calls are implicitly parallelized and pipelined. Simulation provides the task dependency graph and performance numbers for the mapping, which can be done at run time to facilitate data dependent branching. The result is an easy to program, platform independent framework which shields the user from the parallel implementation and mapping of his application, while efficiently utilizing on-chip memory and interconnect bandwidth.

In this paper, we propose an interactive instruction system named IMPRESSION, which allows performance of interactive presentations using multimedia educational materials in class. In recent years, although many practices of educational methodology with information technology and presentation tools using multimedia resources as educational materials have come into common use, instructors can only present such materials in a slide-sheet form through the use of such presentation tools in class. Therefore, instructors can neither do formative evaluations nor can they present suitable materials according to students' reactions in class. Our proposed methodology employs a scenario-based approach in a double loop instructional design process to overcome such problems. Instructors design an instructional plan as a scenario, and subsequently implement and modify the plan through formative evaluation during the class. They then conduct a summative evaluation based on planned and implemented instructions for redesign. To realize our methodology, in this paper we propose and design an instruction system that provides functions to select and present multimedia materials interactively provided on the Internet during the class; we then record these instructions. After implementing it, we confirmed that we can conduct the class flexibly based on our methodology through its practical use in an actual classroom environment.

We devised an efficient architecture of deblocking filter and implemented the circuit with 15,400 logic gates and a 16032 dual-port SRAM using 0.25 µm standard cell technology. This circuit can process 88 image frames with 1,280720 pixels per second at 166 MHz. Our circuit requires smaller number of accesses to the external memory than other approaches and hence causes less bus traffic in the SoC design platform.

Multi-context FPGAs allow very quick reconfiguration by storing multiple configuration data at the same time. While testing for FPGAs with single-context memories has already been studied by many researchers, testing for multi-context FPGAs has not been proposed yet. This paper presents an architecture of testable multi-context FPGAs. In the proposed multi-context FPGA, configuration data stored in a context can be copied into another context. This paper also shows testing of the proposed multi-context FPGA. The proposed testing uses the testing for the traditional FPGAs with single-context. The testing is capable of detecting single stuck-at faults and single open faults which affect normal operations. The number of test configurations for the proposed testing is at most two more than that for the testing of FPGAs with single-context memories. The area overhead of the proposed architecture is 7% and 4% of the area of a multi-context FPGA without the proposed architecture when the number of contexts in a configuration memory is 8 and 16, respectively.

This paper presents a design method of multi-stage, multi-way microstrip power dividers with the aim of constructing a compact low-loss power divider with numbers of outputs. First, an integration design technique of power dividers composed of multi-step, multi-furcation and mitered bends is described. Since the analytical technique is founded on the planar circuit approach combined with the segmentation method, the optimization of the circuit patterns can be performed in a reasonable short computation time. Next, the present method is applied to the design of broadband Nn-way power dividers such as 32-way power divider consisting of 3-way dividers in two-stage structures, respectively. In addition, a 12-way power divider constructed from a series connection of a 3-way and three 4-way dividers is designed. The dividers equivalently contain a 3-section Chebyshev transformer to realize broadband properties. As a result, the fractional bandwidths of nearly 85% and 66.7% for the power-split imbalance less than 0.2 dB and the return loss better than -20 dB are obtained for the 9- and 12-way power dividers, respectively. The validity of these design results is confirmed by a commercial em-simulator (Ansoft HFSS) and experiments.

Orthogonal Arrays (OAs) have been playing important roles in the field of experimental design. It has been known that OAs are closely related to error-correcting codes. Therefore, many OAs can be constructed from error-correcting codes. But these OAs are suitable for only cases that equal interaction effects can be assumed, for example, all two-factor interaction effects. Since these cases are rare in experimental design, we cannot say that OAs from error-correcting codes are practical. In this paper, we define OAs with unequal strength. In terms of our terminology, OAs from error-correcting codes are OAs with equal strength. We show that OAs with unequal strength are closer to practical OAs than OAs with equal strength. And we clarify the relation between OAs with unequal strength and unequal error-correcting codes. Finally, we propose some construction methods of OAs with unequal strength from unequal error-correcting codes.

With the increasing demand for SoCs to include rich functionality, SoCs are being designed with hundreds of small memories with different sizes and frequencies. If memory BIST logics were individually added to these various memories, the area overhead would be very high. To reduce the overhead, memory BIST logic must therefore be shared. This paper proposes a memory-grouping method for memory BIST logic sharing. A memory-grouping problem is formulated and an algorithm to solve the problem is proposed. Experimental results show that the proposed method reduced the area of the memory BIST wrapper by up to 40.55%. The results also show that the ability to select from two types of connection methods produced a greater reduction in area than using a single connection method.

This paper concerns the design, implementation and subsequent experimental validation of a low-voltage analog CMOS switch based on a gate-bootstrapped method. The main part of the proposed circuit is a new low-voltage and low-stress CMOS clock voltage doubler. Through the use of a dummy switch, the charge injection induced by the bootstrapped switch is greatly reduced resulting in improved sample-and-hold accuracy. An important attribute of the design is that the ON-resistance is nearly constant. A test chip has been designed and fabricated using a TSMC 0.18 µm CMOS process (single poly, n-well) to confirm the operation of the circuit for a supply voltage of down to 0.65 V.

A novel variable-length code (VLC), called alternate VLC (AVLC), is proposed, which employs two types of VLC to encode source symbols alternately. Its advantage is that it can not only stop the symbol error propagation effect, but also correct symbol insertion errors and symbol deletion errors, which is very important in video communication.

Recently, system level design languages (SLDL), which can describe both hardware and software aspects of the design, are receiving attention. Mixed-signal extensions of SLDL enable current discrete-oriented SLDLs to describe and simulate not only digital systems but also digital-analog mixed-signal systems. The synchronization between discrete and continuous behaviors is widely regarded as a critical part in the extensions. In this paper, we present an event-driven synchronization mechanism for both timed and untimed system level designs through which discrete and continuous behaviors are synchronized via AD events and DA events. We also demonstrate how the synchronization mechanism can be incorporated into the kernel of SLDL, such as SpecC. In the extended kernel, a new simulation cycle, the AMS cycle, is introduced. Three case studies show that the extended SpecC-based system level design environment using our synchronization mechanism works well with timed/untimed mixed-signal system level description.