Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose low power adders that adaptively select supply voltages based on the input vector patterns. First, we apply the proposed scheme to the Ripple Carry Adder (RCA). A prototype design by a 0.18 µm CMOS technology shows that the Adaptive VDD 32-bit RCA achieves 25% power improvement over the conventional RCA with similar speed. The proposed adder cancels out the delay penalty, utilizing two innovative techniques: carry-skip techniques on the checking operands, and the use of Complementary Pass Transistor Logic (CPL) with dual supply voltage for level conversion. As an expansion to faster adder architectures, we extend the proposal to the Carry-Select Adders (CSA) composed of the RCA sub-blocks. We achieved 24% power improvement on the 128-bit CSA prototype over a conventional design. The proposed scheme also achieves stand-by leakage power reduction--for 32-bit and 128-bit Adaptive RCA and CSA, respectively, 62% and 54% leakage reduction was possible.

A novel interconnect design concept named "ASIS (Appilication-specific Interconnect Structure)" is presented for 45 nm CMOS performance maximization. Basic scheme of ASIS is that corresponding to applications, such as high-performance, low-power, or high reliability, interconnect structure as well as metal thickness is individually optimized in order to maximize chip-level performance matched to the application. Our investigation shows that for low-power application, the increased resistivity of scaled-down Cu-wire is not a main issue, so that thinner wire is more advantageous. For high-performance application, partially double pitch structure for local and intermediate layers is advantageous. For high-reliability requirement, Cu-Al alloy or CoWP cap-metal is quite effective for boosting reliability.

The transport network paradigm is changing as evidenced by IP convergence and the divergence of architectures and technologies. Harnessing the full power of light will spur the creation of new broadband and ubiquitous services networks. To attain this, however, not only must photonic technologies be optimized, but they must also be coordinated with complementary electrical technologies. With regard to photonic network design technologies, further developments are necessary including very large scale network design, quasi-dynamic network design, and multi-layer optical path network design.

Due to the exponentially increasing threat of cyber attacks, many e-commerce organizations around the world have begun to recognize the importance of information security. When considering the importance of security in e-commerce, we need to train e-commerce security experts who can help ensure the reliable deployment of e-commerce. The purpose of this research is to design and evaluate an e-commerce security curriculum useful in training e-commerce security experts. In this paper, we use a phase of the Delphi method and the Analytic Hierarchy Process (AHP) method. To validate our results, we divide the respondents into two groups and compare the survey results.

A novel high-speed and low-voltage CMOS level shifter circuit is proposed. The proposed circuit is suitable for block-level dynamic voltage and frequency scaling (DVFS) environment or multiple-clock and multiple-power-domain logic blocks. In order to achieve high performance in a chip consisting of logic blocks having different VDD voltages, the proposed circuit uses the circuit techniques to reduce the capacitive loading of input signals and to minimize the contention between pull-up and pull-down transistors through positive feedback loop. The techniques improve the slew rate of output signals, so that the level transient delay and duty distortions can be reduced. The proposed level up/down shifters are designed to operate over a wide range of voltage and frequency and verified with Berkeley's 65 nm CMOS model parameters, which can cover a voltage range from 0.6 to 1.6 V and at least frequency range up to 1000 MHz within 3% duty errors. Through simulation with Berkeley's 65 nm CMOS model parameters, the level shifter circuits can solve the duty distortion preventing them from high speed operation within the duty ratio error of 3% at 1 GHz. For verification through performance comparison with reported level shifts, the simulations are carried out with 0.35 µm CMOS technology, 0.13 µm IBM CMOS technology and Berkeley's 65 nm CMOS model parameters. The compared results show that delay time and duty ratio distortion are improved about 68% and 75%, respectively.

We consider a problem for constructing a minimum cost r-edge-connected multigraph in which degree d(v) of each vertex v ∈ V is specified. In this paper, we propose a 3-approximation algorithm for this problem under the assumption that edge cost is metric, r(u,v) ∈ {1,2} for each u,v ∈ V, and d(v) ≥ 2 for each v ∈ V. This problem is a generalization of metric TSP. We also propose an approximation algorithm for the digraph version of the problem.

This paper is intended to provide an alternative approach for the design of FIR filters by using a Hopfield Neural Network (HNN). The proposed approach establishes the error function between the amplitude response of the desired FIR filter and the designed one as a Lyapunov energy function to find the HNN parameters. Using the framework of HNN, the optimal filter coefficients can be obtained from the output state of the network. With the advantages of local connectivity, regularity and modularity, the architecture of the proposed approach can be applied to the design of differentiators and Hilbert transformer with significantly reduction of computational complexity and hardware cost. As the simulation results illustrate, the proposed neural-based method is capable of achieving an excellent performance for filter design.

This paper deals with a design problem of an observer-based robust preview control system for uncertain discrete-time systems. In this approach, we adopt 2-stage design scheme and we derive an observer-based robust controller with integral and preview actions such that a disturbance attenuation level is satisfactorily small for allowable uncertainties.

A tri-template-based codes (TTBC) method is proposed to reduce test cost of intellectual property (IP) cores. In order to reduce test data volume (TDV), the approach utilizes three templates, i.e., all 0, all 1, and the previously applied test data, for generating the subsequent test data by flipping the inconsistent bits. The approach employs a small number of test channels I to supply a large number of internal scan chains 2I-3 such that it can achieve significant reduction in test application time (TAT). Furthermore, as a non-intrusive and automatic test pattern generation (ATPG) independent solution, the approach is suitable for IP core testing because it requires neither redesign of the core under test (CUT) nor running any additional ATPG for the encoding procedure. In addition, the decoder has low hardware overhead, and its design is independent of the CUT and the given test set. Theoretical analysis and experimental results for ISCAS 89 benchmark circuits have proven the efficiency of the proposed approach.

This paper presents a formal design of arithmetic circuits using an arithmetic description language called ARITH. The key idea in ARITH is to describe arithmetic algorithms directly with high-level mathematical objects (i.e., number representation systems and arithmetic operations/formulae). Using ARITH, we can provide formal description of arithmetic algorithms including those using unconventional number systems. In addition, the described arithmetic algorithms can be formally verified by equivalence checking with formula manipulations. The verified ARITH descriptions are easily translated into the equivalent HDL descriptions. In this paper, we also present an application of ARITH to an arithmetic module generator, which supports a variety of hardware algorithms for 2-operand adders, multi-operand adders, multipliers, constant-coefficient multipliers and multiply accumulators. The language processing system of ARITH incorporated in the generator verifies the correctness of ARITH descriptions in a formal method. As a result, we can obtain highly-reliable arithmetic modules whose functions are completely verified at the algorithm level.

A unified representation for various kinds of speculations and global scheduling algorithms is presented. After introducing several types of local and global speculations, reviewing our conventional method called conditional vector-based list scheduling, and discussing some of its limitations, we introduce the unique notion of generalized condition vectors (GCVs), which can represent most varieties of speculations and multiple branches as a single vector. The unification of parallel branches and partially unresolved nested conditional branches is discussed. Then, a scheduling algorithm using GCVs is proposed. Experimental results show the effectiveness of the GCV-based scheduling method.

Recently, system level design languages (SLDLs), which can describe both hardware and software aspects of the design, are receiving attentions. Analog mixed-signal (AMS) extensions to SLDLs enable current discrete-oriented SLDLs to describe and simulate not only digital systems but also digital-analog mixed-signal systems. In this paper, we present our work on the AMS extension to one of the system level design language--SpecC. The extended language supports designer to describe all the analog, digital and software aspects in a universal language.

Combinatorial designs have been used to construct digital fingerprint codes. Here, a new constructive algorithm for an anticollusion fingerprint code based on group-divisible designs is presented. These codes are easy to construct and available for a large number of individuals, which is important from a business point of view. Group-divisible designs have not been used previously as a tool for fingerprint code construction.

In this paper, we compare two signal designs for uplink quasi-synchronous code division multiple access (CDMA) channels in order to optimize the trade-off between bandwidth efficiency and power efficiency. The design we call band-limited DS/CDMA design, is based on the time-domain assignment of Gold sequences, just as in the ordinary DS/CDMA, but with band-constrained cyclic chip interpolation functions, which is unlike the ordinary DS/CDMA. The other design, MC/CDMA design, is based on frequency-domain assignment of the sequences, as in the ordinary MC/CDMA. In both designs, we assume insertion of guard intervals at the transmitter and frequency-domain processing in reception. Assuming quasi-synchronous arrival of CDMA signals at the CDMA base station and FFT in the effective symbol interval, the intersymbol interference is evaded in both designs. First we identified the signal parameters that optimize bandwidth efficiency in each of the band-limited DS design and MC design. Second, we clarified the signal parameters that optimize the power efficiency as functions of frequency efficiency in each of the two designs. Finally, we derived and compared the trade-off between the bandwidth efficiency and power efficiency of band-limited DS and MC designs. We found a superiority of band-limited DS design over MC design with respect to the optimized trade-off.

This paper presents an automated design of analog circuits starting with idealized elements. Our system first synthesizes circuits using idealized elements by a genetic algorithm (GA). GA evolves circuit topologies and transconductances of idealized elements to achieve the given specifications. The use of idealized elements effectively reduces search space and make the synthesis efficient. Second, idealized elements in a generated circuit are replaced by MOSFETs. Through the two processes, a circuit satisfying the given specifications can be obtained. The capability of this method was demonstrated through experiments of synthesis of a trans-impedance amplifier and a cubing circuit and benchmark tests. The results of the benchmark tests show the proposed CAD is more than 10 times faster than the CAD which does not use idealized elements.

A NULL-convention circuit based on dual-rail current-mode differential logic is proposed for a high-performance asynchronous VLSI. Since input/output signals are mapped to dual-rail current signals, the NULL-convention circuit can be directly implemented based on the dual-rail differential logic, which results in the reduction of the device counts. As a typical example, a NULL-convention logic based full adder using the proposed circuit is implemented by a 0.18 µm CMOS technology. Its delay, power dissipation and area are reduced to 61 percent, 60 percent and 62 percent, respectively, in comparison with those of a corresponding CMOS implementation.

A highly collision-resistive RFID system multiplexes communications between thousands of transponders and a single reader using TH-CDMA based anti-collision scheme. This paper focuses on the back-end design consideration of such an RFID system with the deployment of high-level modeling techniques, accompanying a technical comparison of physical-level description, hardware-based emulation, and software-based simulation. A new rapid-prototyping simulation system was constructed to evaluate the robustness of a multiplexed RFID link system with more than 1,000 channels in the presence of field disturbances, and the design parameters of the back-end digital signal processing that dominated anti-collision performance were explored. Finally, the derived optimum parameters were applied to the design of a back-end digital integrated circuit to be installed in collision-resistive transponder circuitry.

A family of sequences with zero correlation zone, which is shortly called a ZCZ set, can provide CDMA system without co-channel interference nor influence of multipath. This paper presents two types of ZCZ sets of non-binary sequence pairs, which achieve the upper bound of family size for length and zero correlation zone. One, which is produced by use of a perfect complementary pair and an orthogonal code, can change zero correlation zone, while the upper bound is kept. The other, which is generated by use of a newly defined orthogonal pair and an orthogonal code, can offer such CDMA system as a binary ZCZ set seems to be used.

This paper presents a design method to minimize energy of both functional units (FUs) and an interconnection network between FUs. To reduce complexity of the interconnection network, data transfers between FUs are classified according to FU types of operations in a data flow graph. The basic idea behind reducing the complexity of the interconnection network is that the interconnection resource can be shared among data transfers with the same FU type of a source node and the same FU type of a destination node. Moreover, an efficient method based on a genetic algorithm is presented.

A novel wiring design concept called "Triple Damascene" is presented. We propose a new technology to mix wirings with different thickness in one layer by using dual damascene process without increasing mask steps. In this technology, three types of grooves are opened simultaneously. Deep trenches for thick wires, as well as vias and shallow trenches, are selectively opened. By the design concept using this technology, a 30% reduction in wiring delay is obtained for critical path. A 5% reduction in chip size is also obtained as the effect of decrease in repeater number for a typical high-performance multi-processing unit (MPU) in 0.13 µm generation. An example for performance enhancement in an actual product of graphic MPU chip is also demonstrated.