Refactoring is one of the promising techniques for improving software design by means of behavior-preserving structural transformation, and is widely taken into practice. In particular, it is frequently applied to design models represented with UML such as class diagrams. However, since UML design models includes multiple diagrams which are closely related from various views, to get behavior-preserving property, we should get the other types of design information and should handle with the propagation of the change on a diagram to the other diagrams. For example, to refactor a class diagram, we need behavioral information of methods included in the class and should also refactor diagrams which represent the behavior, such as state diagrams, activity diagrams. In this paper, we introduce refactoring on design models as transformations of a graph described by UML class diagram and action semantics. First, we define basic transformations of design models that preserve the behavior of designed software, and compose them into refactoring operations. We use Object Constraint Language (OCL) to specify when we can apply a refactoring operation. Furthermore we implement our technique on a graph transformation system AGG to support the automation of refactoring, together with evaluation mechanism of OCL expressions. Some illustrations are presented to show its effectiveness. The work is the first step to handle with refactoring on UML design models in integrated way.

A power-aware interconnect circuit design--called µI/O architecture--has been developed to provide low-cost system solutions for System-on-Chip (SoC) and System-in-Package (SiP) technologies. The µI/O architecture provides a common interface throughout the module enabling hierarchical I/O design for SoC and SiP. The hierarchical I/O design allows the driver size to be optimized without increasing design complexity. Moreover, it includes a signal-level converter for integrating wide-voltage-range circuit blocks and a signal wall function for turning off each block independently--without invalid signal transmission--by using an internal power switch.

This paper presents a Quiet-Noisy scan technique for low power delay fault testing. The novel scan cell design provides both the quiet and noisy scan modes. The toggling of scan cell outputs is suppressed in the quiet scan mode so the power is saved. Two-pattern tests are applied in the noisy scan mode so the delay fault testing is possible. The experimental data shows that the Quiet-Noisy scan technique effectively reduces the test power to 56% of that of the regular scan. The transition fault coverage is improved by 19.7% compared to an existing toggle suppression low power technique. The presented technique requires very minimal changes in the existing MUX-scan Design For Testability (DFT) methodology and needs virtually no computation. The penalties are area overhead, speed degradation, and one extra control in test mode.

This letter handles symbolic simulation for high-level hardware design descriptions including uninterpreted functions. Two new heuristics are introduced, which are named "symbolic function table" and "synchronization". In the experiment, the equivalence of a hardware/software codesign was checked up to a given finite number of cycles, which is composed of a behavioral design, that is, a small DSP program written in C, and its register-transfer-level implementation, a VLIW architecture with an assembly program. Our symbolic simulator succeeded in checking the equivalence of the two descriptions which were not tractable without the heuristics.

In this paper, we propose a preemptive test scheduling technique (a test can be interrupted and later resumed) for core-based systems with the objective to minimize the test application time. We make use of reconfigurable core test wrappers in order to increase the flexibility in the scheduling process. The advantage with such a wrapper is that it is not limited to a single TAM (test access mechanism) bandwidth (wrapper chain configuration) at each core. We model the scheduling problem as a Bin-packing problem, and we discuss the transformation: number of TAM wires (wrapper-chains) versus test time in combination with preemption, as well as the possibilities and the limitations to achieve an optimal solution in respect to test application time. We have implemented the proposed preemptive test scheduling algorithm, and we have through experiments demonstrated its efficiency.

This paper proposes an SoC test architecture generation framework. It contains a database, which stores the test cost information of several DFTs for every core, and a DFT selection part which performs DFT selection for minimizing the test application time using this database in the early phase of the design flow. Moreover, the DFT selection problem is formulated and the algorithm that solves this problem is proposed. Experimental results show that bottlenecks in test application time when using a single DFT method for all cores in an SoC is reduced by performing DFT selection from two types of DFTs. As a result, the whole test application time is drastically shortened.

This paper provides a review on the optimal design of photonic bandgap structures by inverse problem techniques. An overview of inverse problems techniques is given, with a special focus on topology design methods. A review of first applications of inverse problems techniques to photonic bandgap structures and waveguides is given, as well as some model problems, which provide a deeper insight into the structure of the optimal design problems.

In order to transport an ever-increasing amount of IP traffic effectively, Photonic IP networks that employ wavelength routing and Layer 3 cut-through are very important. This paper proposes a new network design algorithm that minimizes the network cost considering IP traffic growth for multi-layered photonic IP networks that comprise electrical label switched paths (LSPs) and optical LSPs. We evaluate the network cost obtained from the developed network design algorithm that considers IP traffic growth and compare it to the results obtained from a static zero-based algorithm. The static zero-based algorithm does not take into account the history of progressive past IP traffic changes/growth until that time. The results show that our proposed algorithm is very effective; the cost increase from the cost obtained using the zero-based algorithm is marginal. The algorithm developed herein enables effective multi-layered photonic IP network design that can be applied to practical networks where IP traffic changes/increases progressively and that can be used for long term network provisioning.

The present paper introduces a new construction of a class of binary sequence set having a zero-correlation zone (hereafter binary zcz sequence set). The cross-correlation function and the side-lobe of the auto-correlation function of the proposed sequence set is zero for the phase shifts within the zero-correlation zone. This paper shows that such a construction generates a binary zcz sequence set from an arbitrary pair of Hadamard matrices of common size. Since the proposed sequence construction generates a sequence set from an arbitrary pair of Hadamard matrices, many more types of sequence sets can be generated by the proposed sequence construction than is possible by a sequence construction that generates sequence sets from a single arbitrary Hadamard matrix.

As the CMOS technology enters the very deep submicron era, inter-wire coupling capacitance becomes the dominant part of load capacitance. The coupling effects have brought new challenges to routing algorithms on both delay estimation and optimization. In this paper, we propose a timing-driven global routing algorithm with consideration of coupling effects. Our two-phase algorithm based on timing-relax method includes a heuristic Steiner tree algorithm to guarantee the timing performance of the initial solution and an optimization algorithm based on coupling-effect-transference. Experimental results are given to demonstrate the efficiency and accuracy of the algorithm.

We analyze the timing design methodology for testing chips using a multiple-clock domain scheme. We especially focus on the layout design of the design-for-test (DFT) circuits and the clock network. First, we demonstrate the built-in-self-testing (BIST) scheme for multiple-clock domains. Then, we discuss the layout method that achieves a low clock-skew between different clock domains with a small modification of the original user logic layout. Finally, we evaluate the fault coverage of our large ASIC chips designed using our new methodology. The short design period and high fault coverage of our methodology are confirmed using actual industrial designs. We introduce a viable approach for industrial designs because designers don't have to pay much attention to DFT. Our approach also provides designers with an easy method for LSI debugging and diagnostics.

In an LSI design process, Engineering Change Orders (ECO's) are often given even after the layout process. This letter presents an approach to change the design to satisfy the new specification with ECO's by employing an error diagnosis technique. Our approach performs incremental synthesis using spare cells embedded on the original layout. Experimental results show that applying the error diagnosis technique to incremental synthesis is effective to suppress increase in delay time caused by ECO's.

This paper presents a variable pipeline depth processor, which can dynamically adjust its pipeline depth and operating voltage at run-time, we call dynamic pipeline and voltage scaling (DPVS), depending on the workload characteristics under timing constraints. The advantage of adjusting pipeline depth is that it can eliminate the useless energy dissipation of the additional stalls, or NOPs and wrong-path instructions which would increase as the pipeline depth grow deeper in excess of the inherent parallelism. Although dynamic voltage scaling (DVS) is a very effective technique in itself for reducing energy dissipation, lowering supply voltage also causes performance degradation. By combining with dynamic pipeline scaling (DPS), it would be possible to retain performance at required level while reducing energy dissipation much further. Experimental results show the effectiveness of our DPVS approach for a variety of benchmarks, reducing total energy dissipation by up to 64.90% with an average of 27.42% without any effect on performance, compared with a processor using only DVS.

This paper experimentally investigates the effectiveness of regularly-placed bit-slice layout and transistor-level optimization to datapath circuit performance. We focus on cell-base design flows with transistor-level circuit optimization. We examine the effectiveness through design experiments of 32-bit carry select adder and 16-bit tree-style multiplier in a 0.35 µm technology. From the experimental results, we can scarcely observe that manual cell placement contributes to improve circuit performance. On the other hand, transistor-level circuit optimization is so effective that circuit delay is reduced by 11-20% and power dissipation decreases to 42-62%. We can see that, in the case of cell-base design, transistor-level optimization is also important as well as in the case of custom design, whereas cell-base bit-slice layout has less importance to circuit performance.

This paper proposes an efficient method for design space exploration of the global optimum configuration for parameterized ASIPs. The method not only guarantees the optimum configuration, but also provides robust speedup for a wide range of processor architectures such as SoC, ASIC as well as ASIP. The optimization procedure within this method takes a two-steps approach. Firstly, design parameters are partitioned into clusters of inter-dependent parameters using parameter dependency information. Secondly, parameters are optimized for each cluster, the results of which are merged for global optimum. In such optimization, inferior configurations are extensively pruned with a detailed optimality mapping between dependent parameters. Experimental results with mediabench applications show an optimization speedup of 4.1 times faster than the previous work on average, which is significant improvement for practical use.

A two stage non-scan design for testability method is proposed. The first stage selects test points based on an earlier testability measure conflict. A new design for testability algorithm is proposed to select test points by a fault-oriented testability measure conflict+ in the second stage. Test points are selected in the second stage based on the hard faults after the initial ATPG run of the design for testability circuit in the preliminary stage. The new testability measure conflict+ based on conflict analysis of hard-faults in the process of test generation is introduced, which emulates most general features of sequential ATPG. The new testability measure reduces testability of a fault to the minimum D or controllability of the primary outputs, and therefore, does not need observability measure any more. Effective approximate schemes are adopted to get reasonable estimation of the testability measure. A couple of effective techniques are also adopted to accelerate the process of the proposed design for testability algorithm. Experimental results show that the proposed method gets even better results than two of the recent non-scan design for testability methods nscan and lcdft.

A special group of voice application services (VASs) are promising contents for wireless as well as wireline networks. Without a designated call admission policy, VAS calls are expected to suffer from relatively high probability of blocking since they normally require better signal quality than ordinary voice calls. In this letter, we consider a prioritized call admission design in order to reduce the blocking probability of VAS calls, which makes the users feel the newly-provided VAS in belief. The VAS calls are given a priority by reserving a number of channel-processing hardwares. With the reservation, the blocking probability of prioritized VAS calls can be evidently reduced. That of ordinary calls, however, is increasing instead. This letter provides a system model that counts the blocking probabilities of VAS and ordinary calls simultaneously, and numerically examines an adequate level of the prioritization for VAS calls.

This letter presents a lower bound and approximation for the coverage probability of the pilot channel that can be used for a CDMA downlink design. The approximation of a compound truncated Poisson distribution is used to obtain a closed form equation for the coverage probability of the pilot channel. Computer simulations show that our lower bound curve is truly less than the empirical curve, and our proposed approximation agrees well with the empirical result.

In this paper an algorithm based on Ant Colony Optimization techniques called Ants on a Tree (AOT) is introduced. This algorithm can integrate many algorithms together to solve a single problem. The strength of AOT is demonstrated by solving a High-Level Synthesis problem. A High-Level Synthesis problem consists of many design steps and many algorithms to solve each of them. AOT can easily integrate these algorithms to limit the search space and use them as heuristic weights to guide the search. During the search, AOT generates a dynamic decision tree. A boosting technique similar to branch and bound algorithms is applied to guide the search in the decision tree. The storage explosion problem is eliminated by the evaporation of pheromone trail generated by ants, the inherent property of our search algorithm.

The software rejuvenation is a proactive fault management technique for operational software systems which age due to the error conditions that accrue with time and/or load, and is important for high assurance systems design. In this paper, fine-grained shock models are developed to determine the optimal rejuvenation policies which maximize the system availability. We introduce three kinds of rejuvenation schemes and calculate the optimal software rejuvenation schedules maximizing the system availability for respective schemes. The stochastic models with three rejuvenation policies are extentions of Bobbio et al. (1998, 2001) and represent the failure phenomenon due to the exhaustion of the software resources caused by the memory leak, the fragmentation, etc. Numerical examples are devoted to compare three control schemes quantitatively.