In this paper, we present a high-performance VC-1 main-profile decoder for high-definition (HD) video applications, which can decode HD 720p video streams with 30 fps at 80 MHz. We implemented the decoder with a one-poly eight-metal 0.13 µm CMOS process, which contains about 261,900 logic gates and on-chip memories of 13.9 KB SRAM and 13.1 KB ROM and occupies an area of about 5.1 mm2. In designing the VC-1 decoder, we used a template-based SoC design flow, with which we performed the design space exploration of the decoder by trying various configurations of communication channels. Moreover, we also describe architectures of the computation blocks optimized to satisfy the requirements of VC-1 HD applications.

Bolstering survivable backbone networks against multiple failures is becoming a common concern among telecom companies that need to continue services even when disasters occur. This paper presents a multiple-failure recovery scheme that considers the operation and management of optical paths. The presented scheme employs scheme escalation from pre-planned restoration to full rerouting. First, the survivability of this scheme against multiple failures is evaluated considering operational constraints such as route selection, resource allocation, and the recovery order of failed paths. The evaluation results show that scheme escalation provides a high level of survivability even under operational constraints, and this paper quantitatively clarifies the impact of these various operational constraints. In addition, the fundamental functions of the scheme escalation are implemented in the Generalized Multi-Protocol Label Switching control plane and verified in an optical-cross-connect-based network.

This paper studies the impact of dummy fill for chemical mechanical polishing (CMP)-induced capacitance variation on buffer insertion based on a virtual CMP fill estimation model. Compared with existing methods, our algorithm is more feasible by performing buffer insertion not in post-process but during early physical design. Our contributions are threefold. First, we introduce an improved fast dummy fill amount estimation algorithm based on [4], and use some speedup techniques (tile merging, fill factor and amount assigning) for early estimation. Second, based on some reasonable assumptions, we present an optimum virtual dummy fill method to estimate dummy position and the effect on the interconnect capacitance. Then the dummy fill estimation model was verified by our experiments. Third, we use this model in early buffer insertion after layer assignment considering the effects of dummy fill. Experimental results verified the necessity of early dummy fill estimation and the validity of our algorithm. Buffer insertion considering dummy fill during early physical design is necessary and our algorithm is promising.

In this letter, we propose combinatorial and search construction methods of 2-D multi-weight optical orthogonal codes (OOCs) with autocorrelation 0 and crosscorrelation 1, called multi-weight single or no pulse per row (MSNPR) codes. An upper bound on the size of MSNPR codes is derived and the performance of MSNPR codes is compared to those of other OOCs in terms of the bit error rate (BER) and evaluated using blocking probability. It is also demonstrated that the MSNPR codes can be flexibly constructed for different applications, providing the scalability to optical CDMA networks.

This letter presents a novel framework in high-level synthesis where hardware modules synthesized from functions in a given ANSI-C program can call the other software functions in the program. This enables high-level synthesis from C programs that contains calls to hard-to-synthesize functions, such as dynamic memory management, I/O request, or very large and complex functions. A single-thread implementation scheme is shown, whose correctness has been verified through register transfer level simulation.

Threshold Inverter Quantization (TIQ) technique has been gaining its importance in high speed flash A/D converters due to its fast data conversion speed. It eliminates the need of resistor ladders for reference voltages generation which requires substantial power consumption. The key to TIQ comparators design is to generate 2n - 1 different sized TIQ comparators for an n-bit A/D converter. This paper presents a highly efficient TIQ comparator design methodology based on an analytical model as well as SPICE simulation experimental model. One can find any sets of TIQ comparators efficiently using the proposed method. A 6-bit TIQ A/D converter has been designed in a 0.18 µm standard CMOS technology using the proposed method, and compared to the previous measured results in order to verify the proposed methodology.

In this paper, an alternative approach is presented, to design equalizers (or matching networks) with commensurate (or equal length) transmission lines. The new method automatically yields the matching network topology with characteristic impedances of the commensurate lines. In the implementation process of the new technique first, the driving point impedance data of the matching network is generated by tracing a pre-selected transducer power gain shape, without optimization. Then, it is modelled as a realizable bounded-real input reflection coefficient in Richard domain, which in turn yields the desired equalizer topology with line characteristic impedances. This process results in an excellent initial design for the commercially available computer aided design (CAD) packages to generate final circuit layout for fabrication. An example is given to illustrate the utilization of the new method. It is expected that the proposed design technique is employed as a front-end, to commercially available computer aided design (CAD) packages which generate the actual equalizer circuit layout with physical dimensions for mass production.

In this letter, new families of binary low correlation zone (LCZ) sequences based on the interleaving technique and quadratic form sequences are constructed, which include the binary LCZ sequence set derived from Gordon-Mills-Welch (GMW) sequences. The constructed sequences have the property that, in a specified zone, the out-of-phase autocorrelation and cross-correlation values are all equal to -1. Due to this property, such sequences are suitable for quasi-synchronous code-division multiple access (QS-CDMA) systems.

Design by Contract (DBC), originated in the Eiffel programming language, is generally accepted as a practical method for building reliable software. Currently, however, few languages have built-in support for it. In recent years, several methods have been proposed to support DBC in Java. We compare eleven DBC tools for Java by analyzing their impact on the developer's programming activities, which are characterized by seven quality attributes identified in this paper. It is shown that each of the existing tools fails to achieve some of the quality attributes. This motivates us to develop ezContract, an open source DBC tool for Java that achieves all of the seven quality attributes. ezContract achieves streamlined integration with the working environment. Notably, standard Java language is used and advanced IDE features that work for standard Java programs can also work for the contract-enabled programs. Such features include incremental compilation, automatic refactoring, and code assist.

We propose Isochronous-MAC (I-MAC) using the Long-Wave Standard Time Code (so called "wave clock"), and introduce cross-layer design for a low-power wireless sensor node with I-MAC. I-MAC has a periodic wakeup time synchronized with the actual time, and thus we take the wave clock. However, a frequency of a crystal oscillator varies along with temperature, which incurs a time difference among nodes. We present a time correction algorithm to address this problem, and shorten the time difference. Thereby, the preamble length in I-MAC can be minimized, which saves communication power. For further power reduction, a low-power crystal oscillator is also proposed, as a physical-layer design. We implemented I-MAC on an off-the-shelf sensor node to estimate the power saving, and verified that the proposed cross-layer design reduces 81% of the total power, compared to Low Power Listening.

Rapid advances in semiconductor manufacturing technology have led to higher chip power densities, which places greater emphasis on packaging and temperature control during testing. For system-on-chips, peak power-based scheduling algorithms have been used to optimize tests under specified power constraints. However, imposing power constraints does not always solve the problem of overheating due to the non-uniform distribution of power across the chip. This paper presents a TAM/Wrapper co-design methodology for system-on-chips that ensures thermal safety while still optimizing the test schedule. The method combines a simplified thermal-cost model with a traditional bin-packing algorithm to minimize test time while satisfying temperature constraints. Furthermore, for temperature checking, thermal simulation is done using cycle-accurate power profiles for more realistic results. Experiments show that even a minimal sacrifice in test time can yield a considerable decrease in test temperature as well as the possibility of further lowering temperatures beyond those achieved using traditional power-based test scheduling.

MD5 is a cryptographic algorithm used for authentication. When implemented in hardware, the performance is affected by the data dependency of the iterative compression function. In this paper, a new functional description is proposed with the aim of achieving higher throughput by mean of reducing the critical path and latency. This description can be used in similar structures of other hash algorithms, such as SHA-1, SHA-2 and RIPEMD-160, which have comparable data dependence. The proposed MD5 hardware architecture achieves a high throughput/area ratio, results of implementation in an FPGA are presented and discussed, as well as comparisons against related works.

Testing PLLs (phase-locked loops) is becoming an important issue that affects both time-to-market and production cost of electronic systems. Though a PLL is the most common mixed-signal building block, it is very difficult to test due to internal analog blocks and signals. In this paper, we propose a new PLL BIST (built-in self test) using the distorted frequency detector that uses only internal digital signals. The proposed BIST does not need to load any analog nodes of the PLL. Therefore, it provides an efficient defect-oriented structural test scheme, reduced area overhead, and improved test quality compared with previous approaches.

This paper performs application-level QoS and user-level QoS assessment of audio-video streaming in cross-layer designed wireless ad hoc networks. In order to achieve high QoS at the user-level, we employ link quality-based routing in the network layer and media synchronization control in the application layer. We adopt three link quality-based routing protocols: OLSR-SS (Signal Strength), AODV-SS, and LQHR (Link Quality-Based Hybrid Routing). OLSR-SS is a proactive routing protocol, while AODV-SS is a reactive one. LQHR is a hybrid protocol, which is a combination of proactive and reactive routing protocols. For application-level QoS assessment, we performed computer simulation with ns-2 where an IEEE 802.11b mesh topology network with 24 nodes was assumed. We also assessed user-level QoS by a subjective experiment with 30 assessors. From the assessment results, we find AODV-SS the best for networks with long inter-node distances, while LQHR outperforms AODV-SS for short inter-node distances. In addition, we also examine characteristics of the three schemes with respect to the application-level QoS in random topology networks.

This letter addresses the problem of robust transceiver design for the multiuser multiple-input-multiple-output (MIMO) downlink where the channel state information at the base station (BS) is imperfect. A stochastic approach which minimizes the expectation of the total mean square error (MSE) of the downlink conditioned on the channel estimates under a total transmit power constraint is adopted. The iterative algorithm reported in [2] is improved to handle the proposed robust optimization problem. Simulation results show that our proposed robust scheme effectively reduces the performance loss due to channel uncertainties and outperforms existing methods, especially when the channel errors of the users are different.

The deep submicron semiconductor technologies will make the worst-case design impossible, since they can not provide design margins that it requires. We are investigating a typical-case design methodology, which we call the Constructive Timing Violation (CTV). This paper extends the CTV concept to collapse dependent instructions, resulting in performance improvement. Based on detailed simulations, we find the proposed mechanism effectively collapses dependent instructions.

In the optimum design of AC contactors, it is important to analyze the dynamic behavior. Moreover, movable contact and core bounces have remarkable effect on the lifetime of contactors. According to a new kind of contactor with feedback controlled magnet system, this paper builds two different sets of periodically inter-transferred equations to obtain the dynamic characteristics of the contactor. The equations describe the coupling of the electric circuit, electromagnetic field and mechanical system taking account of the influence of friction. Then, the paper gives an optimum design to the dimension and the duty ratio of the contactor' pulse modulated wave (PWM) under different exciting, and proves, by experiment and simulation, that the bounce time of the contactor working in the optimized duty ratio is much less than that of the general AC contactors.

This paper simulates the dynamic behavior of the operating mechanism of ACB, and analyzes factors influencing the mechanism's operating time. First, it builds a dynamic model for the mechanism with virtual prototype technology. Experiment validation is carried out to prove the correctness of the model. Based on this model, it puts emphasis on analyzing the influence of electro-dynamic repulsion force on the operating time of the mechanism. Simulation and experimental results show that after adding electric repulsion force to the model, the operating time is shortened about 1.1 ms. Besides the repulsion force, other influencing factors including the stiffness of opening spring, locations of every key axis, mass and centroidal coordinates of every mechanical part are analyzed as well. Finally, it makes an optimum design for the mechanism. After optimization, the velocity of operating mechanism is improved about 6.7%.

The present paper introduces the construction of a class of sequence sets with zero-correlation zones called zero-correlation zone sequence sets. The proposed zero-correlation zone sequence set can be generated from an arbitrary perfect sequence and an arbitrary Golay complementary sequence pair. The proposed construction is a generalization of the zero-correlation zone sequence construction previously reported by the present author. The proposed sequence set can successfully provide CDMA communication without co-channel interference.

The IEEE 1500 standard wrapper requires that its inputs and outputs be interfaced directly to the chip's primary inputs and outputs for controllability and observability. This is typically achieved by providing a dedicated Test Access Mechanism (TAM) between the wrapper and the primary inputs and outputs. However, when reusing the embedded Network-on-Chip (NoC) interconnect instead of the dedicated TAM, the standard wrapper cannot be used as is because of the packet-based transfer mechanism and other functional requirements by the NoC. In this paper, we describe two NoC-compatible wrappers, which overcome these limitations of the 1500 wrapper. The wrappers (Type 1 and Type 2) complement each other to optimize NoC bandwidth utilization while minimizing the area overhead. The Type 2 wrapper uses larger area overhead to increase bandwidth efficiency, while Type 1 takes advantage of some special configurations which may not require a complex and high-cost wrapper. Two wrapper optimization algorithms are applied to both wrapper designs under channel-bandwidth and test-time constraints, resulting in very little or no increase in the test application time compared to conventional dedicated TAM approaches.