This paper describes the effects of system LSI design with C language-based behavioral synthesis following several trials of design period reduction and quality improvement for a variety of circuit types. The results of these trials are analyzed from the viewpoints of description productivity, verification productivity, reusability and design flexibility as well as hardware and software co-verification. First the C-based design flow proposed by the authors is described, and the design productivity and verification productivity under this design flow is compared to RTL design. The reusability of the behavioral IP core and its efficiency with HW/SW co-verification are also shown using design examples. Next, using the example of an MPEG-4 video decoder design, a typical design process in a C-based design is shown with considerations regarding verification efficiency, reusability of the IP core and HW/SW co-verification. Finally, the authors' perspectives regarding future directions of system LSI design are discussed.

An automated synthesis for analog computational circuits in transistor-level configuration is presented. A cell-based structure is introduced to place moderate constraints on the MOSFET circuit topology. Even though each cell has a simple structure that consists of one current path with four transistors, common analog building blocks can be implemented using combinations of the cells. A genetic algorithm is applied to search circuit topologies and transistor sizes that satisfy given specifications. Synthesis capabilities are demonstrated through examples of three types of computational circuits; absolute value, squaring, and cubing functions by using computer simulations and real hardware.

This paper discusses two types of polyphase sequence sets, which will successfully provide CDMA systems without co-channel interference. One is a type of ZCZ sets, whose periodic auto-correlation functions take zero at continuous shifts on both side of the zero-shift, and periodic cross-ones also take zero at the continuous shifts and the zero-shift. The other is a new type of sets consisting of some subsets of polyphase sequences with zero cross-correlation zone, called ZCCZ sets, whose periodic cross-correlation functions among different subsets have take zero at continuous shifts on both side of the zero-shift including the zero-shift. The former can achieve a mathematical bound, and the latter can have large size.

A great deal of effort has been spent to develop strategies for allocation of resources in DS-CDMA systems in order to mitigate effects of interference between users. Here, the choice of spreading sequences and appropriate power allocation play a crucial role. When developing such strategies, CDMA system designers need to ensure that each user meets its quality-of-service requirement expressed in terms of the signal-to-interference+noise ratio. We say that a set of users is admissible in a CDMA system if one can assign sequences to the users and control their power so that all users meet their quality-of-service requirements. In [1], the problem of admissibility in a synchronous CDMA channel was solved. However, since the simplistic setting of perfect symbol synchronism rarely holds in practice, there is a strong need for investigating asynchronous CDMA channels. In this paper, we consider a K-user asynchronous CDMA channel with processing gain N and identical performance requirements for all users assuming chip synchronism. We solve the problem of admissibility of the users in such a channel if N K, and identify optimal sequences. We also show that constant power allocation is optimal. Results obtained in this paper give valuable insights into the limits of asynchronous CDMA systems.

This paper devises a sophisticated approach to the performance estimation of an embedded hardware-software codesign system at the architecture level, which intends to optimize the hardware-software configuration in terms of processing time, power dissipation, and hardware cost. A distinctive feature of this approach consists in constructing a performance estimation model proper to each component of an embedded system, such as CPU core, RAM/ROM, cache memory, and application-specific hardware, by taking account of not only the functional performance but also the data transfer. The proposed estimation schemes are incorporated into an existing instruction set simulator, so that the actual performance can be estimated accurately at the architecture level. The experimental results demonstrate that the performance estimation approach enables the precise design decision at the architecture level, which greatly contributes toward enhancing the design ability dedicatedly for mobile appliances.

In this paper, a VLSI architecture for lifting-based discrete wavelet transform (LDWT) is presented. Our architecture folds the computations of all resolution levels into the same low-pass and high-pass units to achieve higher hardware utilization. Due to the regular and flexible structure of the design, its area is independent of the length of the 1-D input sequence, and its latency is independent of the number of resolution levels. For the computations of analysis process of N-sample 1-D 3-level LDWT, our design takes about N clock cycles and requires 2 multipliers, 4 adders, and 22 registers. It is fabricated with TSMC 0.35-µm cell library and has a die size of 1.21.2 mm2. The power dissipation of the chip is about 0.4 W at the clock rate of 80 MHz.

This paper presents a novel system-level design methodology, called quality-driven design, by which application-specific optimization can be achieved; furthermore the entire functionality can be shared to maximize design reuse. As a case of study, this paper focuses on quality-driven design for video applications and introduces an output quality adaptive approach based on variable bitwidth optimization to explore a new design space. MPEG2 video is used as the driver application to illustrate the potential of the presented methodology. Experimental results show the effectiveness of the methodology.

2-Factor covering designs, a type of combinatorial designs, have recently received attention since they have industrial applications including software testing. For these applications, even a small reduction on the size of a design is significant, because it directly leads to the reduction of testing cost. In this letter, we report ten new designs that we constructed, which improve on the previously best known results.

This paper presents a case study of synthesis of the industrial embedded microcontroller HT48100 and analysis of performance, cost and software compatibility for its implementation alternatives, using the hardware/software co-design system for microcontrollers/microprocessors PIPER-II. The synthesis tool accepts as input the instruction set architecture (behavioral) specification, and produces as outputs the pipelined RTL designs with their simulators, and the reordering constraints which guide the compiler backend to optimize the code for the synthesized designs. A compiler backend is provided to optimize the application software according to the reordering constraints. The study shows that the co-design approach was able to help the original design team to analyze the architectural properties, identify inefficient architecture features, and explore possible architectural improvements and their impacts in both hardware and software. Feasible future upgrades for the microcontroller family have been identified by the study.

This paper discusses a design methodology suitable for the development of software defined radio platforms. A flexible digital receiver was designed and implemented using a multi-port direct converter and an FPGA-based platform. The design starts with a hardware-oriented top-level system model. The model is built based on basic signal processing blocks connected together in a graphical tool. Carrier symbol timing recovery is implemented in the discrete-time (digital) domain with an interpolator-based synchronizer. Carrier phase and frequency are recovered using a feedback synchronization algorithm (a second-order type-II digital PLL). Experimental results of the platform and its simulation results demonstrate the effectiveness of the proposed design methodology.

This paper proposes a compiler generation method for PEAS-III (Practical Environment for ASIP development), which is a configurable processor development environment for application domain specific embedded systems. Using the PEAS-III system, not only the HDL description of a target processor but also its target compiler can be generated. Therefore, execution cycles and dynamic power consumption can be rapidly evaluated. Two processors and their derivatives were designed using the PEAS-III system in the experiment. Experimental results show that the trade-offs among area, performance and power consumption of processors were analyzed in about twelve hours and the optimal processor was selected under the design constraints by using generated compilers and processors.

As a design flow for low-power FPGA implementation, Datapath-Layout-Driven Design (DLDD) has been proposed. This letter reports the effect of DLDD for standard-cell-based ASIC implementation, and proposes necessary improvements. Experimental results shows that about 8.3% reduction of power dissipation is achieved in the best case.

In this letter, our proposed approach exploits the use of original and simplest Cellular Neural Network (CNN) for 2D Doubly Complementary (DC) Infinite Impulse Response (IIR) filter banks design. The properties of feedback and feedforward templates are studied for this purpose. Through some examples it is shown how generalizations of these templates can be used for DC IIR filter banks design. We modify Lagrangian function which is used for optimizing a low-pass filter design considering the constraint for stability of CNN. The brief conclusions with design examples that illustrate the proposed method and an image enhancement and restoration applications of designed filter banks are presented.

This letter presents text-independent speaker identification results for telephone speech. A speaker identification system based on Karhunen-Loeve transform (KLT) derived from codebook design using genetic algorithm (GA) is proposed. We have combined genetic algorithm (GA) and the vector quantization (VQ) algorithm to avoid typical local minima for speaker data compression. Identification accuracies of 91% were achieved for 100 Mandarin speakers.

In this paper a new MOS charge pump architecture is presented, where a clock generator is used in each pump stage of the charge pump circuit to elevate voltage exponentially with stages. This charge pump with a clock level shifter is designed to run at an optimized operation frequency, which can make an excellent compromise between the rise time and the dynamic power dissipation. With less stages than the linear-cascade circuit, the power dissipation and the area of the novel charge pump circuit are markedly decreased. The simulating comparison results based on 1.2 µm CMOS, p-substrate double-poly double-metal process parameters show that the nonlinear charge pump with a high pumping efficiency can supply a steady 1 mA, 16 v output for portable LCDs.

This paper deals with formal verification of high-level designs, in particular, symbolic comparison of register-transfer-level descriptions and behavioral descriptions. We use state machines extended by quantifier-free first-order logic with equality, as models of those descriptions. We cannot adopt the classical notion of equivalence for state machines, because the signals in the corresponding outputs of such two descriptions do not change in the same way. This paper defines a new notion of consistency based on signal-transitions of the corresponding outputs, and proposes an algorithm for checking consistency of those descriptions, up to a limited number of steps from initial states. As an example of high-level designs, we take a simple hardware/software codesign. A C program for digital signal processing called PARCOR filter was compared with its corresponding design given as a register-transfer-level description, which is composed of a VLIW architecture and assembly code. Since this example terminates within approximately 4500 steps, symbolic exploration of a finite number of steps is sufficient to verify the descriptions. Our prototype verifier succeeded in the verification of this example in 31 minutes.

This paper presents a comprehensive investigation of three optical wavelength-division multiplexed (WDM) mesh network protection approaches, namely minimal cost, single link basis and disjoint path approaches. The operation of each approach is described and their performances are extensively evaluated and compared. Key aspects that are taken into the consideration and comparison of the designs include a spare capacity requirement, ease of operation and practical feasibility. A mathematical model based on integer linear programming is introduced to obtain a lower bound on the spare capacity requirement for full protection against all single link failures. Two heuristic algorithms have also been developed to perform wavelength resource allocation under both normal and failure conditions for both systems with and without wavelength conversion capability. It is shown that the minimal cost approach can accomplish the lowest extra cost requirement for protection, but this approach is considered not appropriate for practical applications due to complicated restoration and management. The single link basis scheme is on the other hand more practical and very cost efficient. For the disjoint path technique, the cost for spare capacity is generally slightly greater than that of the single link basis scheme. Its main advantages lie in the simple re-configuration and inherent protection against node failure for in-transit traffic. Finally, a new framework for obtaining a good spare capacity cost estimate of a mesh restorable network is presented.

Load/unload techniques are widely used in mobile hard disk drives which have to endure external shocks frequently. ABS designs must consider both the load/unload performance and the shock resistance performance. Three ABS designs with different positions of the suction force center are studied in simulation. It is observed that when the position of the suction force center moves frontward, the anti-shock performance improves, but the unload performance degrades, and vice versa. A slider is not necessary to be designed to have its suction force center significantly behind of its geometric center, as the traditional load/unload sliders do. Instead, the suction force center can be designed near the geometric center if the hook limiter is used.

Unlike in existing mobile networks, a variety of services having different quality requirements will be provided in future mobile networks, where any single group of service users can not characterize the whole traffic distribution in the system. Beginning at the mobile network design, the population of service subscribers is estimated and then base stations are located. As the service market evolves, the volume of users might grow or the population of users distributed between the multiple services as well as the located cells might change. In this case, two questions are of interest: how much growth in user population and what change in user distribution can be accommodated in the current cell configuration. If such shifts could not be admitted, current frequency and base station allocations should be expanded or reallocated. In this paper, we provide a framework that can decide whether the present network configuration is able to admit the changes of interest. Admissibility decision rules are addressed with proofs.

ZCZ sets are families of sequences, whose periodic auto/cross-correlation functions have zero correlation zone at the both side of the zero-shift. They can provide approximately synchronized CDMA systems without intra-cell interference for cellular mobile communications. This paper presents ternary ZCZ sets achieving a mathematical bound, and investigates the average interference parameters for the sets in order to evaluate inter-cell interference. It is shown that they can provide AS-CDMA systems with efficiency frequency usage.