The objective of this paper is to analyze a pull type multi-product, multi-line and multi-stage flexible manufacturing system whose resources are subject to planned and unplanned breakdown conditions. To ensure a continual supply of the finished products, under breakdown conditions, parts/materials flow through alternate routes exhibiting routing flexibility. The machine resources are flexible in this study and are capable of producing more than one item. Every machining and assembly station has been equipped with automated inspection units to ensure the quality of the products. The system is modelled through coloured Petri net methodology and the impact of input factors have been shown on the performance of the system. The study has been extended to explore near-optimal conditions of the system using design of experiment and response surface methods.

Full-diversity transmission for space-time block codes (STBCs) with multiple transmit antennas can be achieved by using coordinate interleaved orthogonal designs (CIODs). To effectively evaluate the performance of CIODs, we derive union upper and lower bounds on the symbol-error rate (SER) and a corresponding asymptotic diversity order of symmetric structured CIOD, in particular, with two transmit antennas over quasi-static spatially uncorrelated/correlated frequency-nonselective Rayleigh fading channels. Some numerical results are provided to verify our analysis.

In this paper, we present a new fast Fourier transform (FFT) algorithm to reduce the table size of twiddle factors required in pipelined FFT processing. The table size is large enough to occupy significant area and power consumption in long-point FFT processing. The proposed algorithm can reduce the table size to half, compared to the radix-22 algorithm, while retaining the simple structure. To verify the proposed algorithm, a 2048-point pipelined FFT processor is designed using a 0.18 µm CMOS process. By combining the proposed algorithm and the radix-22 algorithm, the table size is reduced to 34% and 51% compared to the radix-2 and radix-22 algorithms, respectively. The FFT processor occupies 1.28 mm2 and achieves a signal-to-quantization-noise ratio (SQNR) of more than 50 dB.

Decision diagrams are often used for efficient representation of discrete functions in terms of needed storage space and processing time. In this paper, we propose an XML (Extensible Markup Language) based standard for the structural description of various types of decision diagrams. The proposed standard describes elements of the structure common to various types of decision diagrams. It also provides facilities for storing additional information, specific to particular types of decision diagrams. Properties of XML enable us to define a standard that is flexible enough to be applicable to various existing types of decision diagrams as well as new types that could be defined in the future. The existence of such a standard permits efficient storage and exchange of data in decision diagram form between various software systems. In this way, it supports benchmarking, testing and verification of various procedures using decision diagrams as a basic data structure.

We review practical case studies of a developing method of highly reliable real-time embedded control systems using a CPU model-based hardware/software co-simulation. We take an approach that enables us to fully simulate a virtual mechanical control system including a mechatronics plant, microcontroller hardware, and object code level software. This full virtual system approach simulates control system behavior, especially that of the microcontroller hardware and software. It enables design space exploration of microarchitecture, control design validation, robustness evaluation of the system, software optimization before components design. It also avoids potential problems. The advantage of this work is that it comprises all the components in a typical control system, enabling the designers to analyze effects from different domains, for example mechanical analysis of behavior due to differences in controller microarchitecture. To further improve system design, evaluation and analysis, we implemented an integrated behavior analyzer in the development environment. This analyzer can graphically display the processor behavior during the simulation without affecting simulation results such as task level CPU load, interrupt statistics, and the software variable transition chart. It also provides useful information on the system behavior. This virtual system analysis does not require software modification, does not change the control timing, and does not require any processing power from the target microcontroller. Therefore this method is suitable for real-time embedded control system design, in particular automotive control system design that requires a high level of reliability, robustness, quality, and safety. In this study, a Renesas SH-2A microcontroller model was developed on a CoMETTMplatform from VaST Systems Technology. An electronic throttle control (ETC) system and an engine control system were chosen to prove this concept. The electronic throttle body (ETB) model on the Saber® simulator from Synopsys® and the engine model on MATLAB®/Simulink® simulator from MathWorks can be simulated with the SH-2A model using a newly developed co-simulation interface between MATLAB®/Simulink® and CoMETTM. Though the SH-2A chip was being developed as the project was being executed, we were able to complete the OSEK OS development, control software design, and verification of the entire system using the virtual environment. After releasing a working sample chip in a later stage of the project, we found that such software could run on both actual ETC system and engine control system without critical problem. This demonstrates that our models and simulation environment are sufficiently credible and trustworthy.

The present paper introduces an integrated construction of binary sequences having a zero-correlation zone. The cross-correlation function and the side-lobe of the auto-correlation function of the proposed sequence set is zero for the phase shifts within the zero-correlation zone. The proposed method enables more flexible design of the binary zero-correlation zone sequence set with respect to its member size, length, and width of zero-correlation zone. Several previously reported sequence construction methods of binary zero-correlation zone sequence sets can be explained as special cases of the proposed method.

This paper proposes a new type of compact waveguide directional coupler, which is constructed from two crossed E-plane rectangular waveguide with two metallic posts in the square junction and one metallic post at each port. The metallic posts in the square junction are set symmetrically along a diagonal line to obtain the directivity properties. The metallic post inserted at each input/output waveguide port can realize a matched state. Tight-coupling properties 0.79-6 dB are realized by optimizing the dimension of the junction and the positions/radii of the posts. The design results are verified by an em-simulator (Ansoft HFSS) and experiments.

Web services (WS, hereafter) paradigm has attained such a relevance in both the academic and the industry world that the vision of the Internet has evolved from being considered as a mere repository of data to become the underlying infrastructure on which organizations' strategic business operations are being deployed [1]. Security is a key aspect if WS are to be generally accepted and adopted. In fact, over the past years, the most important consortiums of the Internet, like IETF, W3C or OASIS, have produced a huge number of WS-based security standards. Despite this spectacular growth, a development process that facilitates the systematic integration of security into all subprocesses of WS-based software development life-cycle does not exist. Eventually, this process should guide WS-based software developers in the specification of WS-based security requirements, the design of WS-based security architectures, and the deployment of the most suitable WS security standards. In this article, we will briefly present a process of this type, named PWSSec (Process for Web Services Security), and the artifacts used during the elicitation activity, which belongs to the subprocess WSSecReq aimed at producing a WS-based security requirement specification.

IP (Intellectual Property) reuse plays an important role in modern IC design so that IP Protection (IPP) technique is get concerned. In this paper, we introduce a new efficient watermarking system for IPP on post-layout design stage. The signature (which indicates the designer) is encrypted with a secret key by DES (Data Encryption Standard) to produce a bit string, which is then embedded into the layout design as constraints by using a specific incremental router. Once the design is watermarked successfully, the signature can be extracted accurately by the system. The system also has a strong resistance to the attack on watermarking due to the DES functionality. This watermarking technique uniquely identifies the circuit origin, yet is difficult to be detected or fabricated without our tool. We evaluated the watermarking system on IBM-PLACE 2.0 benchmark suites. The results show the system robustness and strength: the system success probability achieves 100% in suitable time with no extra area and wire length cost on design performances.

The specification of a Multi-Agent System (MAS) involves the identification of a large number of entities and their relationships. This is a non-trivial task that requires managing different views of the system. Many problems concerning this issue originate in the presence of contradictory goals and tasks, inconsistencies, and unexpected behaviours. Such troublesome configurations should be detected and prevented during the development process in order to study alternative ways to cope with them. In this paper, we present methods and tools that support the management of contradictions during the analysis and design of MAS. Contradiction management in MAS has to consider both individual (i.e. agent) and social (i.e. organization) aspects, and their dynamics. Such issues have already been considered in social sciences, and more concretely in the Activity Theory, a social framework for the study of interactions in activity systems. Our approach applies knowledge from Activity Theory in MAS, especially its base of contradiction patterns. That requires a formalization of this social theory in order to be applicable in a software engineering context and its adaptation to agent-oriented methodologies. Then, it will be possible to check the occurrence of contradiction patterns in a MAS specification and provide solutions to those situations. This technique has been validated by implementing an assistant for the INGENIAS Development Kit and has been tested with several case studies. This paper shows part of one of these experiments for a web application.

Recently, space-time block codes (STBCs) obtained from coordinate interleaved orthogonal designs (CIODs) have attracted considerable attention, due to the advantages of full-diversity transmission and single-symbol decodability. In this letter, we design a novel STBC from CIOD for two transmit antennas. The proposed code guarantees full-diversity and full-rate along with low peak-to-minimum power ratio (PMPR). Furthermore, in contrast to the existing Alamouti code, the performance of the proposed code is not degraded even in severely time-selective fading channels.

Various trajectories of design, arising from the new methodology of analog network design, are analyzed. Several major criteria suggested for optimal selection of initial approximation to the design process permit the minimization of computer time. The initial approximation point is selected with regard to the previously revealed effect of acceleration of the design process. The concept of separatrix is defined making it possible to determine the optimal position of the initial approximation. The numerical results obtained for passive and active networks prove the possibility of optimal choice of the initial point in design process.

As semiconductor processing technology advances, complex, high density circuits can be integrated in a chip. However, increasing energy consumption is becoming one of the most important limiting factors. Power estimation at the early stage of design is essential since design changes at later stages may significantly lengthen the design period and increase the costs. For efficient power estimation, we analyze the "key" control signals of a digital circuit and develop power models for several operational modes. The trade-off between accuracy and complexity can be made by choosing the number and the complexity of the power models. When compared with those of logic simulation based estimation, experimental results show that 13 to 15 times faster power estimation with an estimation error of about 5% is possible. We have also developed new logic-level power modeling techniques in which logic gates are levelized and several levels are selected to build power model tables. This table based method shows significant improvement in estimation accuracy and a slight improvement in efficiency when compared to a well-known previous method. The average estimation error has been reduced from 13.3% to 3.8%.

The ESIGN signature scheme was initially proposed in 1985. Since then, several variants have been proposed, but only a few have been formally supported using the methodology of provable security. In addition, these schemes are different from the ESIGN-PSS signature scheme submitted to ISO/IEC-14888-2 for standardization. It is believed that ESIGN-PSS is secure against the chosen-message attack, however, there has not yet been any report verifying this belief. This paper presents the security proofs of ESIGN-PSS and a variant of this scheme, denoted ESIGN-PSS-R, which is a signature scheme comprising the ESIGN signature mechanism and the PSS-R mechanism.

For the optimization design of air circuit breaker (ACB), it is important and necessary to calculate the electro-dynamic repulsion force acting on the movable contact. A method based on 3-D FEM with the equations that describe the relationships among current, magnetic field and repulsion force, which takes the ferromagnet into account, is adopted to calculate the electro-dynamic repulsion force. The method enables one to analyze the factors that affect the electro-dynamic repulsion force, including the number of the movable conductor parallel branches as well as the location of the axis and the shape of the flexible connection. The discussion of the calculation results is also presented in this paper.

This paper presents a novel method to increase an impedance of a current source. The proposed circuit with a cascode and gain-boosting configuration is also presented. The operation has been confirmed by simulation using a 0.18 µm CMOS technology.

This paper presents an automated design of linear and non-linear differential analog circuits accelerated by reuse of genetic operations. The system first synthesizes circuits using pairs of simplified MOSFET model. During the evolutionary process, genetic operations that improve circuit characteristics are stored in a database and reused to effectively obtain a better circuit. Simplified elements in a generated circuit are replaced by MOSFETs and optimization of the transistor size is performed using an optimizer available in market if necessary. The capability of this method is demonstrated through experiments of synthesis of a differential voltage amplifier, a circuit having cube-law characteristic in differential mode and square-law characteristic in common-mode, and a dB-linear VGA (Variable Gain Amplifier). The results show the reuse of genetic operations accelerates the synthesis and success rate becomes 100%.

A new method of cancellation of IM3 using current feedback has been proposed for a multi-stage RFIC amplifier. In order to cancel the IM3 present in an output signal of the amplifier, the IIP3 level and IM3 phase of the amplifier are adjusted by means of feedback circuit techniques, so that the target specification is satisfied. By estimating the IIP3 level and IM3 phase variations for two states in situations with and without feedback possessing linear factors, the parameters of a feedback circuit can be calculated. To confirm the validity of the method, we have investigated two approaches; one including an analytical approach to designing a two-stage feedback amplifier, achieving an IIP3 level improvement of 14.8 dB. The other method involves the fabrication of single-stage amplifiers with and without feedback, operating at 850 MHz, both of which were designed as an integrated circuit using a 0.18 µm SiGe BiCMOS process. The fabricated IC's were tested using a load-pull measurement system, and a good agreement between the estimated and measured IIP3 level and IM3 phase variations has been achieved. Further studies show that the error in these variations, as estimated by the method, has been found to be less than 1.5 dB and 15 degrees, respectively, when the load admittance at 1701 MHz was greater than 1/50 S.

The present paper introduces the construction of a class of sequence sets with zero-correlation zones called zero-correlation zone sequence sets. The proposed zero-correlation zone sequence set can be generated from an arbitrary perfect sequence, the length of which is longer than 4. The proposed sets of ternary sequences, which can be constructed from an arbitrary perfect sequence, can successfully provide CDMA communication without co-channel interference. In an ultrasonic synthetic aperture imaging system, the proposed sequence set can improve the signal-to-noise ratio of the acquired image.

A novel interconnect design concept named "ASIS (Appilication-specific Interconnect Structure)" is presented for 45 nm CMOS performance maximization. Basic scheme of ASIS is that corresponding to applications, such as high-performance, low-power, or high reliability, interconnect structure as well as metal thickness is individually optimized in order to maximize chip-level performance matched to the application. Our investigation shows that for low-power application, the increased resistivity of scaled-down Cu-wire is not a main issue, so that thinner wire is more advantageous. For high-performance application, partially double pitch structure for local and intermediate layers is advantageous. For high-reliability requirement, Cu-Al alloy or CoWP cap-metal is quite effective for boosting reliability.