In this paper, an ultra-thin wave absorber using a resistive patch array closely-placed in front of a back-metal is designed. The positively large susceptance is required for the patch array to cancel out the negatively large input susceptance of the short-circuited ultra-thin spacer behind the array. It is found that the array needs the gap of 1mm, sheet resistance of less than 20Ω/sq. and patch width of more than 15mm to obtain the zero input susceptance of the absorber with the 1/30 wavelength spacer. Moreover, these parameters were designed considering the electromagnetic coupling between the array and back-metal, and the square patch array absorbers with the thickness from 1/30 to 1/150 wavelength were designed.

Hardware accelerators are designed to support a specialized processing dataflow for everchanging deep neural networks (DNNs) under various processing environments. This paper introduces two hardware properties to describe the cost of data movement in each memory hierarchy. Based on the hardware properties, this paper proposes a set of evaluation metrics that are able to evaluate the number of memory accesses and the required memory capacity according to the specialized processing dataflow. Proposed metrics are able to analytically predict energy, throughput, and area of a hardware design without detailed implementation. Once a processing dataflow and constraints of hardware resources are determined, the proposed evaluation metrics quickly quantify the expected hardware benefits, thereby reducing design time.

Due to the rapid growth of the information industry, various Internet of Things (IoT) devices have been widely used in our daily lives. Since the demand for low-cost and high-performance hardware devices has increased, malicious third-party vendors may insert malicious circuits into the products to degrade their performance or to leak secret information stored at the devices. The malicious circuit surreptitiously inserted into the hardware products is known as a ‘hardware Trojan.’ How to detect hardware Trojans becomes a significant concern in recent hardware production. In this paper, we propose a hardware Trojan detection method that employs two-stage neural networks and effectively utilizes the Trojan probability of neighbor nets. At the first stage, the 11 Trojan features are extracted from the nets in a given netlist, and then we estimate the Trojan probability that shows the probability of the Trojan nets. At the second stage, we learn the Trojan probability of the neighbor nets for each net in the netlist and classify the nets into a set of normal nets and Trojan ones. The experimental results demonstrate that the average true positive rate becomes 83.6%, and the average true negative rate becomes 96.5%, which is sufficiently high compared to the existing methods.

We propose an algorithm for the constrained design of FIR filters with sparse coefficients. In general filter design approaches, as the length of the filter increases, the number of multipliers used to construct the filter increases. This is a serious problem, especially in two-dimensional FIR filter designs. The FIR filter coefficients designed by the least-squares method with peak error constraint are optimal in the sense of least-squares within a given order, but not necessarily optimal in terms of constructing a filter that meets the design specification under the constraints on the number of coefficients. That is, a higher-order filter with several zero coefficients can construct a filter that meets the specification with a smaller number of multipliers. We propose a two-step approach to design constrained sparse FIR filters. Our method minimizes the number of non-zero coefficients while the frequency response of the filter that meets the design specification. It achieves better performance in terms of peak error than conventional constrained least-squares designs with the same or higher number of multipliers in both one-dimensional and two-dimensional filter designs.

We developed a Nb 4-layer process for fabricating superconducting integrated circuits that involves using caldera planarization to increase the flexibility and reliability of the fabrication process. We call this process the planarized high-speed standard process (PHSTP). Planarization enables us to flexibly adjust most of the Nb and SiO2 film thicknesses; we can select reduced film thicknesses to obtain larger mutual coupling depending on the application. It also reduces the risk of intra-layer shorts due to etching residues at the step-edge regions. We describe the detailed process flows of the planarization for the Josephson junction layer and the evaluation of devices fabricated with PHSTP. The results indicated no short defects or degradation in junction characteristics and good agreement between designed and measured inductances and resistances. We also developed single-flux-quantum (SFQ) and adiabatic quantum-flux-parametron (AQFP) logic cell libraries and tested circuits fabricated with PHSTP. We found that the designed circuits operated correctly. The SFQ shift-registers fabricated using PHSTP showed a high yield. Numerical simulation results indicate that the AQFP gates with increased mutual coupling by the planarized layer structure increase the maximum interconnect length between gates.

A nonvolatile field-programmable gate array (NV-FPGA), where the circuit-configuration information still remains without power supply, offers a powerful solution against the standby power issue. In this paper, an NV-FPGA is proposed where the programmable logic and interconnect function blocks are described in a hardware description language and are pushed through a standard-cell-based design flow with nonvolatile flip-flops. The use of the standard-cell-based design flow makes it possible to migrate any arbitrary process technology and to perform architecture-level simulation with physical information. As a typical example, the proposed NV-FPGA is designed under 55nm CMOS/100nm magnetic tunnel junction (MTJ) technologies, and the performance of the proposed NV-FPGA is evaluated in comparison with that of a CMOS-only volatile FPGA.

Recent trends in designing filters involve development of sparse filters with coefficients that not only have real but also zero values. These sparse filters can achieve a high performance through optimizing the selection of the zero coefficients and computing the real (non-zero) coefficients. Designing an infinite impulse response (IIR) sparse filter is more challenging than designing a finite impulse response (FIR) sparse filter. Therefore, studies on the design of IIR sparse filters have been rare. In this study, we consider IIR filters whose coefficients involve zero value, called sparse IIR filter. First, we formulate the design problem as a linear programing problem without imposing any stability condition. Subsequently, we reformulate the design problem by altering the error function and prepare several possible denominator polynomials with stable poles. Finally, by incorporating these methods into successive thinning algorithms, we develop a new design algorithm for the filters. To demonstrate the effectiveness of the proposed method, its performance is compared with that of other existing methods.

Network service providers need to appropriately design systems and carefully configuring the settings and parameters to ensure that the systems keep running consistently and deliver the desired services. This can be a heavy and error-prone task. Intent-based system design methods have been developed to help with such tasks. These methods receive service-level requirements and generate service configurations to fulfill the given requirements. One such method is search-based system design, which can flexibly generate systems of various architectures. However, it has difficulty dealing with constraints on the quantitative parameters of systems, e.g., disk volume, RAM size, and QoS. To deal with practical cases, intent-based system design engines need to be able to handle quantitative parameters and constraints. In this work, we propose a new intent-based system design method based on search-based design that augments search states with quantitative constraints. Our method can generate a system that meets both functional and quantitative service requirements by combining a search-based design method with constraint checking. Experimental results show that our method can automatically generate a system that fulfills all given requirements within a reasonable computation time.

Advanced information-processing services such as computer vision require a high-performance digital circuit to perform high-load processing at high speed. To achieve high-speed processing, several image-processing applications use an approximate computing technique to reduce idle time of the circuit. However, it is difficult to design the high-speed image-processing circuit while controlling the error rate so as not to degrade service quality, and this technique is used for only a few applications. In this paper, we propose a method that achieves high-speed processing effectively in which processing time for each task is changed by roughly detecting its completion. Using this method, a high-speed processing circuit with a low error rate can be designed. The error rate is controllable, and a circuit design method to minimize the error rate is also presented in this paper. To confirm the effectiveness of our proposal, a ripple-carry adder (RCA), 2-dimensional discrete cosine transform (2D-DCT) circuit, and histogram of oriented gradients (HOG) feature calculation circuit are evaluated. Effective clock periods of these circuits obtained by our method with around 1% error rate are improved about 64%, 6%, and 12%, respectively, compared with circuits without error. Furthermore, the impact of the miscalculation on a video monitoring service using an object detection application is investigated. As a result, more than 99% of detection points required to be obtained are detected, and it is confirmed the miscalculation hardly degrades the service quality.

In a network topology design problem, it is important to analyze the reliability and construction cost of complex network systems. This paper addresses a topological optimization problem of minimizing the total cost of a network system with separate subsystems under a reliability constraint. To solve this problem, we develop three algorithms. The first algorithm finds an exact solution. The second one finds an exact solution, specialized for a system with identical subsystems. The third one is a heuristic algorithm, which finds an approximate solution when a network system has several identical subsystems. We also conduct numerical experiments and demonstrate the efficacy and efficiency of the developed algorithms.

In order to improve tracking, interference and multipath mitigation performance from that possible with existing signals, a new Global Navigation Satellite System (GNSS) signal is needed that can offer additional degrees of freedom for shaping its pulse waveform and spectrum. In this paper, a new modulation scheme called Quinary Offset Carrier modulation (QOC) is proposed as a new GNSS signal design. The pulse waveforms of QOC modulation are divided into two types: convex and concave waveforms. QOC modulations can be easily constructed by selecting different modulation parameters. The spectra and autocorrelation characteristics of QOC modulations are investigated and discussed. Simulations and analyses show that QOC modulation can achieve similar performance to traditional BOC modulation in terms of code tracking, anti-multipath, and compatibility. QOC modulation can provide a new option for satellite navigation signal design.

Z-complementary pairs (ZCPs) were proposed by Fan et al. to make up for the scarcity of Golay complementary pairs. A ZCP of odd length N is called Z-optimal if its zero correlation zone width can achieve the maximum value (N + 1)/2. In this letter, inserting three elements to a GCP of length L, or deleting a point of a GCP of length L, we propose two constructions of Z-optimal ZCPs with length L + 3 and L - 1, where L=2α 10β 26γ, α ≥ 1, β ≥ 0, γ ≥ 0 are integers. The proposed constructions generate ZCPs with new lengths which cannot be produced by earlier ones.

The plain bend in a pair of differential transmission lines causes a path difference, which leads to differential-to-common mode conversion due to the phase difference. This conversion can cause serious common-mode noise issues. We previously proposed a tightly coupled asymmetrically tapered bend to suppress forward differential-to-common mode conversion and derived the constraint conditions for high-density wiring. To provide sufficient suppression of mode conversion, however, the additional correction was required to make the effective path difference vanish. This paper proposes a practical and straightforward design methodology by using a very tightly coupled bend (decreasing the line width and the line separation of the tightly coupled bend). Full-wave simulations below 20GHz demonstrated that sufficient suppression of the forward differential-to-common mode conversion is successfully achieved as designed. Measurements showed that our design methodology is effective.

This paper studies the infinite time horizon optimal control problem for continuous-time nonlinear systems. A completely model-free approximate optimal control design method is proposed, which only makes use of the real-time measured data from trajectories instead of a dynamical model of the system. This approach is based on the actor-critic structure, where the weights of the critic neural network and the actor neural network are updated sequentially by the method of weighted residuals. It should be noted that an external input is introduced to replace the input-to-state dynamics to improve the control policy. Moreover, strict proof of convergence to the optimal solution along with the stability of the closed-loop system is given. Finally, a numerical example is given to show the efficiency of the method.

In the design of electrical contacts, it is required to pursue a solution which satisfies simultaneously multi-objective (electrical, mechanical, and thermal) performances including conflicting requirements. Preference Set-Based Design (PSD) has been proposed as practical procedure of the fuzzy set-based design method. This brief paper newly attempts to propose a concurrent design method by PSD to electrical contact, specifically a design of a shape of cantilever in relay contacts. In order to reduce the calculation (and/or experimental) cost, this paper newly attempt to apply Design of Experiments (DoE) for meta-modeling to PSD. The number of the calculation for the meta-modeling can be reduced to $rac{1}{729}$ by using DoE. The design parameters (width and length) of a cantilever for drive an electrical contact, which satisfy required performance (target deflection), are obtained in ranges successfully by PSD. The validity of the design parameters is demonstrated by numerical modeling.

We propose a new design approach to improve the computational efficiency of an optimal design of optical waveguide devices utilizing coupled mode theory (CMT) and a neural network (NN). Recently, the NN has begun to be used for efficient optimal design of optical devices. In this paper, the eigenmode analysis required in the CMT is skipped by using the NN, and optimization with an evolutionary algorithm can be efficiently carried out. To verify usefulness of our approach, optimal design examples of a wavelength insensitive 3dB coupler, a 1 : 2 power splitter, and a wavelength demultiplexer are shown and their transmission properties obtained by the CMT with the NN (NN-CMT) are verified by comparing with those calculated by a finite element beam propagation method (FE-BPM).

In this paper, we propose a radio frequency (RF) anti-aliasing filter design method considering the effect of a roll-off characteristic on a noise figure (NF) in the direct RF undersampling receiver. The proposed method is useful for broadband reception that a system bandwidth (BW) has nearly half of the sampling frequency (1/2 fs). When the system BW is extended nearly 1/2 fs, the roll-off band is out of the desired Nyquist zone and it affects NF additionally. The proposed method offers a design target regarding the roll-off characteristic not only the rejection ratio. The target is helpful as a design guide to meet the allowed NF. We design the filter based on the proposed method and it is applied to the direct RF undersampling on-board receiver for Ka-band high throughput satellite (HTS). The measured NF value of the implemented receiver almost matched the designed value. Moreover, the receiver achieved the reception bandwidth which is 90% of 1/2 fs.

Over the past two decades, irregular low-density parity-check (LDPC) codes have not been able to decode information corrupted by insertion and deletion (ID) errors without markers. In this paper, we bring to light the existence of irregular LDPC codes that approach the symmetric information rates (SIR) of the channel with ID errors, even without markers. These codes have peculiar shapes in their check-node degree distributions. Specifically, the check-node degrees are scattered and there are degree-2 check nodes. We propose a code construction method based on the progressive edge-growth algorithm tailored for the scattered check-node degree distributions, which enables the SIR-approaching codes to progress in the finite-length regime. Moreover, the SIR-approaching codes demonstrate asymptotic and finite-length performance that outperform the existing counterparts, namely, concatenated coding of irregular LDPC codes with markers and spatially coupled LDPC codes.

Approximate multiplier design is an effective technique to improve hardware performance at the cost of accuracy loss. The current approximate multipliers are mostly ASIC-based and are dedicated for one particular application. In contrast, FPGA has been an attractive choice for many applications because of its high performance, reconfigurability, and fast development round. This paper presents a novel methodology for designing approximate multipliers by employing the FPGA-based fabrics (primarily look-up tables and carry chains). The area and latency are significantly reduced by applying approximation on carry results and cutting the carry propagation path in the multiplier. Moreover, we explore higher-order multipliers on architectural space by using our proposed small-size approximate multipliers as elementary modules. For different accuracy-hardware requirements, eight configurations for approximate 8×8 multiplier are discussed. In terms of mean relative error distance (MRED), the error of the proposed 8×8 multiplier is as low as 1.06%. Compared with the exact multiplier, our proposed design can reduce area by 43.66% and power by 24.24%. The critical path latency reduction is up to 29.50%. The proposed multiplier design has a better accuracy-hardware tradeoff than other designs with comparable accuracy. Moreover, image sharpening processing is used to assess the efficiency of approximate multipliers on application.

This paper describes designing a new pedestrian navigation system using a comprehensive framework called the pedestrian navigation concept reference model (PNCRM). We implement this system as a publicly-available smartphone application and evaluate its positioning performance near Omiya station's western entrance. We also evaluate users' subjective impressions of the system using a questionnaire. In both cases, promising results are obtained, showing that the PNCRM can be used as a tool for designing pedestrian navigation systems, allowing such systems to be created systematically.