The scan segmentation method is an efficient solution to deal with the test power problem; However, the use of multiple capture cycles may cause capture violations, thereby leading to fault coverage loss. This issue is much more severe in at-speed testing. In this paper, two scan partition schemes based on complex networks clustering ara proposed to minimize the capture violations without increasing test-data volume and extra area overhead. In the partition process, we use a more accurate notion, spoiled nodes, instead of violation edges to analyse the dependency of flip-flops (ffs), and we use the shortest-path betweenness (SPB) method and the Laplacian-based graph partition method to find the best combination of these flip-flops. Beyond that, the proposed methods can use any given power-unaware set of patterns to test circuits, reducing both shift and capture power in at-speed testing. Extensive experiments have been performed on reference circuit ISCAS89 and IWLS2005 to verify the effectiveness of the proposed methods.

We reported a secure scan design approach using shift register equivalents (SR-equivalents, for short) that are functionally equivalent but not structurally equivalent to shift registers [10 and also introduced generalized shift registers (GSRs, for short) to apply them to secure scan design [11]-[13]. In this paper, we combine both concepts of SR-equivalents and GSRs and consider the synthesis problem of SR-equivalent GSRs, i.e., how to modify a given GSR to an SR-equivalent GSR. We also consider the enumeration problem of SR-equivalent GFSRs, i.e., the cardinality of the class of SR-equivalent GSRs to clarify the security level of the secure scan architecture.

The goal of software testing should go beyond simply finding defects. Ultimately, testing should be focused on increasing customer satisfaction. Defects that are detected in areas of the software that the customers are especially interested in can cause more customer dissatisfaction. If these defects accumulate, they can cause the software to be shunned in the marketplace. Therefore, it is important to focus on reducing defects in areas that customers consider valuable. This article proposes a value-driven V-model (V2 model) that deals with customer values and reflects them in the test design for increasing customer satisfaction and raising test efficiency.

Designing a backbone IP network, especially to support both unicast and multicast traffic under delay constraints, is a difficult problem. Real network design must consider cost, performance and reliability. Therefore, a simulator can help a network designer to test the functionality of the network before the implementation. This paper proposes a heuristic design algorithm called D-MENTOR, and the algorithm was developed by programming based on Mesh Network Topological Optimization and Routing Version 2 (MENTOR-II) to integrate as a new module of DElite tool. The simulation results show that, in almost all test cases, the proposed algorithm yields lower installation cost.

In our previous work [12], [13], we introduced generalized feed-forward shift registers (GF2SR, for short) to apply them to secure and testable scan design. In this paper, we introduce another class of generalized shift registers called generalized feedback shift registers (GFSR, for short), and consider the properties of GFSR that are useful for secure scan design. We present how to control/observe GFSR to guarantee scan-in and scan-out operations that can be overlapped in the same way as the conventional scan testing. Testability and security of scan design using GFSR are considered. The cardinality of each class is clarified. We also present how to design strongly secure GFSR as well as GF2SR considered in [13].

The orthogonal array is an important object in combinatorial design theory, and it is applied to many fields, such as computer science, coding theory and cryptography etc. This paper mainly studies the existence of the mixed orthogonal arrays of strength two with seven factors and presents some new constructions. Consequently, a few new mixed orthogonal arrays are obtained.

Time performance optimization and resource conflict resolution are two important challenges in multiple project management contexts. Compared with traditional project management, multi-project management usually suffers limited and insufficient resources, and a tight and urgent deadline to finish all concurrent projects. In this case, time performance optimization of the global project management is badly needed. To our best knowledge, existing work seldom pays attention to the formal modeling and analyzing of multi-project management in an effort to eliminate resource conflicts and optimizing the project execution time. This work proposes such a method based on PRT-Net, which is a Petri net-based formulism tailored for a kind of project constrained by resource and time. The detailed modeling approaches based on PRT-Net are first presented. Then, resource conflict detection method with corresponding algorithm is proposed. Next, the priority criteria including a key-activity priority strategy and a waiting-short priority strategy are presented to resolve resource conflicts. Finally, we show how to construct a conflict-free PRT-Net by designing resource conflict resolution controllers. By experiments, we prove that our proposed priority strategy can ensure the execution time of global multiple projects much shorter than those without using any strategies.

This paper presents a novel low-power decoder architecture for the (36420, 32778) binary LDPC code targeting energy-efficient NAND-flash-based mobile devices. The proposed energy-scalable decoding algorithm reduces the operating bit-width of decoding function units at the early-use stage where the channel condition is good enough to lower the precision of computation. Based on a flexible adder structure, the decoding energy of the proposed LDPC decoder can be reduced by freezing the unnecessary parts of hardware resources. A prototype 4KB LDPC decoder is designed in a 65nm CMOS technology, which achieves an average decoding throughput of 8.13Gb/s with 1.2M equivalent gates. The power consumption of the decoder ranges from 397mW to 563mW depending on operating conditions.

The sense of presence, that is, the sense of the website being psychologically transported to the consumer, has been identified as an important factor for bringing back the feeling of sociability and physicality that is lost in online shopping. Previous research has investigated how visual content in the design can influence the sense of presence in a website, but the focus has been limited to the domestic electronic commerce context. In this paper, we conduct an experimental study in a cross-border electronic commerce context to evaluate the effect of country-related pictures on the perception of country presence, visual appeal and trust in a foreign online store. Two experimental conditions were considered: country-related pictures and generic pictures, each one evaluated for Thai and Singaporean websites. It was hypothesized that country-related content in pictures included in the design of the foreign online store would result in a higher level of country presence, and that this would in turn result in higher visual appeal and trust in the website. We conducted a survey among Japanese online consumers, with a total of 1991 participants obtained. The subjects were randomly assigned into four groups corresponding to the combination of country-of-origin of the website and picture condition. We used structural equation modeling in order to analyze the proposed hypotheses. The results showed that for both the Thai and Singaporean websites, country-related pictures resulted in higher country presence, and visual appeal was positively influenced by this increase in country presence. However, country presence did not have a direct effect on trust; this effect was completely mediated by visual appeal. We discuss these results and their implications for cross-border electronic commerce.

This paper addresses the designability of Boolean networks, i.e., the existence of a Boolean function satisfying an attractor condition under a given network structure. In particular, we present here a necessary and sufficient condition of the designability of Boolean networks with multiple attractors. The condition is characterized by the cyclicity of network structures, which allows us to easily determine the designability.

Camellia is a block cipher jointly developed by Mitsubishi and NTT of Japan. It is designed suitable for both software and hardware implementations. One of the design-for-test techniques using scan chains is called scan-path test, in which testers can observe and control the registers inside the LSI chip directly in order to check if the LSI chip correctly operates or not. Recently, a scan-based side-channel attack is reported which retrieves the secret information from the cryptosystem using scan chains. In this paper, we propose a scan-based attack method on the Camellia cipher using scan signatures. Our proposed method is based on the equivalent transformation of the Camellia algorithm and the possible key candidate reduction in order to retrieve the secret key. Experimental results show that our proposed method sucessfully retrieved its 128-bit secret key using 960 plaintexts even if the scan chain includes the Camellia cipher and other circuits and also sucessfully retrieves its secret key on the SASEBO-GII board, which is a side-channel attack standard evaluation board.

There have recently been more and more reports on CMOS integrated circuits operating at terahertz (≥ 0.1THz) frequencies. However, design environments and techniques are not as well established as for RF CMOS circuits. This paper reviews recent progress made by the authors in terahertz CMOS design for low-power and high-speed wireless communication, including device characterization and modeling techniques. Low-power high-speed wireless data transfer at 11Gb/s and 19pJ/bit and a 7-pJ/bit ultra-low-power transceiver chipset are presented.

The Process Virtual Machine (VM) is typical software that runs applications inside operating systems. Its purpose is to provide a platform-independent programming environment that abstracts away details of the underlying hardware, operating system and allows bytecodes (portable code) to be executed in the same way on any other platforms. The Process VMs are implemented using an interpreter to interpret bytecode instead of direct execution of host machine codes. Thus, the bytecode execution is slower than those of the compiled programming language execution. Several techniques including our previous paper, the “Fetch/Decode Hardware Extension”, have been proposed to speed up the interpretation of Process VMs. In this paper, we propose an additional methodology, the “Hardware Extension with Hybrid Execution” to further enhance the performance of Process VMs interpretation and focus on Register-based model. This new technique provides an additional decoder which can classify bytecodes into either simple or complex instructions. With “Hybrid Execution”, the simple instruction will be directly executed on hardware of native processor. The complex instruction will be emulated by the “extra optimized bytecode software handler” of native processor. In order to eliminate the overheads of retrieving and storing operand on memory, we utilize the physical registers instead of (low address) virtual registers. Moreover, the combination of 3 techniques: Delay scheduling, Mode predictor HW and Branch/goto controller can eliminate all of the switching mode overheads between native mode and bytecode mode. The experimental results show the improvements of execution speed on the Arithmetic instructions, loop & conditional instructions and method invocation & return instructions can be achieved up to 16.9x, 16.1x and 3.1x respectively. The approximate size of the proposed hardware extension is 0.04mm2 (or equivalent to 14.81k gates) and consumes an additional power of only 0.24mW. The stated results are obtained from logic synthesis using the TSMC 90nm technology @ 200MHz.

In this paper, we first propose a notion of multiple authorities attribute-based designated confirmer signature scheme with unified verification. In a multiple authorities attribute-based designated confirmer signature scheme with unified verification, both the signer and the designated confirmer can run the same protocols to confirm a valid signature or disavow an invalid signature. Then, we construct a multiple authorities attribute-based designated confirmer signature scheme with unified verification. Finally, we prove the correctness and security of the proposed scheme.

Instrumental variable (IV) filters designed for range sidelobe suppression in multiple-input multiple-output (MIMO) radar suffer from Doppler mismatch. This mismatch causes losses in peak response and increases sidelobe levels, which affect the performance of MIMO radar. In this paper, a novel method using the component-code processing prior to the IV filter design for MIMO radar is proposed. It not only compensates for the Doppler effects in the design of IV filter, but also offers more virtual sensors resulting in narrower beams with lower sidelobes. Simulation results are presented to verify the effectiveness of the method.

In our previous work [12], [13], we introduced generalized feed-forward shift registers (GF2SR, for short) to apply them to secure and testable scan design, where we considered the security problem from the viewpoint of the complexity of identifying the structure of GF2SRs. Although the proposed scan design is secure in the sense that the structure of a GF2SR cannot be identified only from the primary input/output relation, it may not be secure if part of the contents of the circuit leak out. In this paper, we introduce a more secure concept called strong security such that no internal state of strongly secure circuits leaks out, and present how to design such strongly secure GF2SRs.

Studies on gaze analysis have revealed some of the relationships between viewers' gaze and their internal states (e.g., interests and intentions). However, understanding content browsing behavior in uncontrolled environments is still challenging because human gaze can be very complex; it is affected not only by viewers' states but also by the spatio-semantic structures of visual content. This study proposes a novel gaze analysis framework which introduces the content creators' point of view to understand the meaning of browsing behavior. Visual content such as web pages, digital articles and catalogs are comprised of structures intentionally designed by content creators, which we refer to as designed structure. This paper focuses on two design factors of designed structure: spatial structure of content elements (content layout), and their relationships such as “being in the same group”. The framework was evaluated with an experiment involving 12 participants, wherein the participant's state was estimated from their gaze behavior. The results from the experiment show that the use of design structure improved estimation accuracies of user states compared to other baseline methods.

The emerging three-dimensional (3D) technology is considered as a promising solution for achieving better performance and easier heterogeneous integration. However, the thermal issue becomes exacerbated primarily due to larger power density and longer heat dissipation paths. The thermal issue would also be critical once FPGAs step into the 3D arena. In this article, we first construct a fine-grained thermal resistive model for 3D FPGAs. We show that merely reducing the total power consumption and/or minimizing the power density in vertical direction is not enough for a thermal-aware 3D FPGA backend (placement and routing) flow. Then, we propose our thermal-aware backend flow named TherWare considering location-based heat balance. In the placement stage, TherWare not only considers power distribution of logic tiles in both lateral and vertical directions but also minimizes the interconnect power. In the routing stage, TherWare concentrates on overall power minimization and evenness of power distribution at the same time. Experimental results show that TherWare can significantly reduce the maximum temperature, the maximum temperature gradient, and the temperature deviation only at the cost of a minor increase in delay and runtime as compared with present arts.

We demonstrated that load balancing using actual subscriber extension numbers was practical and effective against traffic congestion after a disaster based on actual data. We investigated the ratios of the same subscriber extension numbers in each prefecture and found that most of them were located almost evenly all over the country without being concentrated in a particular area. The ratio of every number except for the fourth-last digit in the last group of four numbers in a telephone number was used almost equally and located almost evenly all over the country. Tolerance against overload in the last, second-, and third-last single digits stays close to that in the ideal situation if we assume that each session initiation protocol server has a capacity in accordance with the ratio of each number on every single digit in the last group of four numbers in Japan. Although tolerance against overload in double-, triple-, and quadruple-digit numbers does not stay close to that in the ideal situation, it still remains sufficiently high in the case of double- and triple-digit numbers. Although tolerance against overload in the quadruple-digit numbers becomes low, disaster congestion is still not likely to occur in almost half of the area of Japan (23 out of 47 prefectures).

Motion estimation (ME) is a key encoding component of almost all modern video coding standards. ME contributes significantly to video coding efficiency, but, it also consumes the most power of any component in a video encoder. In this paper, an ME processor with 3D stacked memory architecture is proposed to reduce memory and core power consumption. First, a memory die is designed and stacked with ME die. By adding face-to-face (F2F) pads and through-silicon-via (TSV) definitions, 2D electronic design automation (EDA) tools can be extended to support the proposed 3D stacking architecture. Moreover, a special memory controller is applied to control data transmission and timing between the memory die and the ME processor die. Finally, a 3D physical design is completed for the entire system. This design includes TSV/F2F placement, floor plan optimization, and power network generation. Compared to 2D technology, the number of input/output (IO) pins is reduced by 77%. After optimizing the floor plan of the processor die and memory die, the routing wire lengths are reduced by 13.4% and 50%, respectively. The stacking static random access memory contributes the most power reduction in this work. The simulation results show that the design can support real-time 720p @ 60fps encoding at 8MHz using less than 65mW in power, which is much better compared to the state-of-the-art ME processor.