This paper proposes a new flexible hardware model for pipelined design optimization. Using together with an RTL floorplanner, the flexible hardware model makes accurate and fine design space exploration possible. It is quite effective for deep submicron technology since estimation at high level has become a difficult problem and the design tuning at lower level of abstraction makes up the full design optimization task. The experimental results show that our approach reduces the slack time in the pipeline stages then achieves higher performance with a smaller area.

This paper reports on an Intelligent CASE tool, applicable in a structured programming phase, or from detailed design to coding. This is automation of the bottom level in the hierarchical design process of detailed design and coding, where the largest man-hours are consumed. The main idea is that human designers use a CASE tool for the initial design of a software system, and the design knowledge is automatically acquired from the structured charts and stored in the knowledge base. The acquired design knowledge may be reused in designs. By reusing it, a similar software system may be designed automatically. It has been shown that knowledge acquired in this way has a Logarithmic Learning Effect. Based on this, a quantitative evaluation of productivity is made. By accumulating design experiences (e. g. 10 times), more than 80% of the detailing designs are performed automatically, and productivity increases by up to 4 times. This tool features universality, an essentially zero start-up cost for automatic design, and a substantial increase in software productivity after enough experiences have been accumulated. This paper proposes a new basic idea and its implementation, a quantitative evaluation applying techniques from Industrial Engineering, which proves the effectiveness of the proposed system.

This paper presents a new routing method that takes into account neighboring-wire-capacitance (inter-layer and intra-layer) constraints. Intermediate routing (IR) assigns each H/V wire segment to the detailed routing (DR) grid using global routing (GR) results, considering the neighboring-wire constraints (NWC) for critical nets. In DR, the results of IR for constrained nets and their neighboring wires are preserved, and violations that occur in IR are corrected. A simple method for setting NWC that satisfy the initial wire capacitance given in a set-wire-load (SWL) file is also presented. The routing method enables more accurate delay evaluation by considering inter-wire capacitance before DR, and avoids long and costly turnaround in deepsubmicron layout design. Experimental results using MCNC benchmark test data shows that the errors between the maximum delay from IR and that from DR for each net were less than 5% for long (long delay) nets.

This paper proposes a new method for dynamically controlling the clock speed of a processor in order to reduce power consumption without decreasing system performance. It automatically tunes the processor's speed by monitoring its activities and avoiding useless work so as not to exhaust the battery energy. Experiments with performance bottlenecks caused by disk activities show that the proposed method is very effective in comparison with the traditional one, in which the processor's speed is fixed.

This paper presents Power-Pro architecture (Programmable Power Management Architecture), a novel processor architecture for power reduction. The Power-Pro architecture has two key functionalities: (i) Supply voltage and clock frequency of a microprocessor can be dynamically varied, and (ii) active datapath width can be dynamically adjusted to the precision of each operation. The most unique point of this architecture is that software programmers can directly specify the requirements of applications such as real-time constraints and precision of the operations. To make programmable power management possible, Power-Pro architecture equips special instructions. Programmers can vary the supply voltage, the clock frequency and the active datapath width dynamically by the instructions. Experimental results show that power consumption for a variety of applications are dramatically reduced by the Power-Pro architecture.

The required building blocks of CMOS fuzzy chips capable of performing as adaptive fuzzy systems are described in this paper. The building blocks are designed with mixed-signal current-mode cells that contain low-resolution A/D and D/A converters based on current mirrors. These cells provide the chip with an analog-digital programming interface. They also perform as computing elements of the fuzzy inference engine that calculate the output signal in either analog or digital formats, thus easing communication of the chip with digital processing environments and analog actuators. Experimental results of a 9-rule prototype integrated in a 2. 4-µm CMOS process are included. It has a digital interface to program the antecedents and consequents and a mixed-signal output interface. The proposed design approach enables the CMOS realization of low-cost and high-inference fuzzy systems able to cope with complex processes through adaptation. This is illustrated with simulated results of an application to the on-line identification of a nonlinear dynamical plant.

Recently, a great deal of effort has been devoted to the design problem of "constrained least squares M-D FIR filter" because a significant improvement of the squared error is expected by a slight relaxation of the minimax error condition. Unfortunately, no design method has been reported, which has some theoretical guarantee of the convergence to the optimal solution. In this paper, we propose a class of novel design methods of "constrained least squares M-D FIR filter. " The most remarkable feature is that all of the proposed methods have theoretical guarantees of convergences to the unique optimal solution under any consistent set of prescribed maximal error conditions. The proposed methods are based on "convex projection techniques" that computes the metric projection onto the intersection of multiple closed convex sets in real Hilbert space. Moreover, some of the proposed methods can still be applied even for the problem with any inconsistent set of maximal error conditions. These lead to the unique optimal solution over the set of all filters that attain the least sum of squared distances to all constraint sets.

For mobile telecommunication systems, it is important to accurately predict the propagation-path loss in terms of the estimation of the radiowave coverage area. The propagation-path loss has been estimated in a median obtained spatially from many received amplitudes (envelopes) within a region of several tens times as long as the wavelength, rather than in the envelopes themselves. Although ray tracing can obtain the envelopes and their median that reflect the site-dependent characteristics, the estimated median sometimes does not agree with the measured one. Therefore, the accuracy improvement has been expected. In this paper, an accuracy improvement is achieved by substituting a median with random phases for the median obtained spatially from many envelopes. The characteristic function method is used to obtain the cumulative distribution function and the median analytically where the phases are randomized. In a multipath environment, the phase-estimation error accompanying the location error of the ray tracing input influences the spatially obtained median. The phase-randomizing operation reduces the effects of the phase-estimation error on the median prediction. According to our estimation, improvements in accuracy of 4. 9 dB for the maximum prediction error and 2. 9 dB for the RMS prediction error were achieved. In addition, a probability-based cell-design method that takes the radiowave arrival probability and the interference probability into consideration is possible by using the percentiles obtained by the characteristic function method and the cell-design examples are shown in this paper.

We present a high-level synthesis scheme that considers weak testability of generated register-transfer level (RTL) data paths, as well as their area and performance. The weak testability, proposed in our previous work, is a testability measure of RTL data paths for non-scan design. In our scheme, we first extract a condition on resource sharing sufficient for weak testability from a data flow graph before synthesis, and treat the condition as design objectives in the following synthesis tasks. We propose heuristic synthesis algorithms which optimize area and the design objectives under the performance constraint.

We will present a partial scan design method based on n-fold line-up structures in order to achieve high fault efficiency and reduce test pattern generation time for practical LSIs. We will also present a partial scan design method based on the state justification of pure load/hold FFs in order to achieve high fault efficiency and reduce the number of scan FFs for practical LSIs with lots of load/hold FFs. Experimental results for practical LSIs show that our presented methods can achieve high fault efficiency (more than 99%) and reduce the number of scan FFs for the LSI with lots of load/hold FFs.

Non-uniform traffic can affect communications quality in microcell systems, and this disparity in communications quality between base stations (BSs) lowers the system efficiency in CDMA systems. If traffic distribution and propagation conditions are already known during the introduction of a CDMA system, it is desirable to design cell areas according to the non-uniformity of traffic distribution and BS locations. Cell area is determined by the transmission power of the pilot-signal from the BS and it is necessary to control the transmission power of mobile stations in the uplink, which is determined by the desired power level at the BS, according to the cell area. The disparity in communications quality can be rectified by optimally designing the two parameters of the pilot-signal power and desired power level. This paper describes an algorithm for setting both the pilot-signal power and the desired power level during the cell design stage in CDMA systems. The proposed algorithm operates that the communications qualities of all BSs in the system converge to average quality by adjusting the two parameters. The parameters of all BSs in the whole system can be determined through computer calculation. Through performance evaluations, we confirmed that the average SIRs of all BSs attained almost the same value and the variance between the BSs was less than half by adopting the cell design algorithm when there was dispersion in BS placement. This algorithm is also effective using the actual measured SIR after a system has been established.

The advantage of random testing is that test application can be performed at a low cost in the BIST scheme. However, not all circuits are random pattern testable due to the existence of random pattern resistant faults. In this paper, we present a method for improving the random pattern testability of logic circuits by partial circuit duplication approach. The basic idea is to detect random pattern resistant faults by using the difference between the duplicated part of a circuit and the original part. Experimental results on benchmark circuits show that high fault coverage can be achieved with a very small amount of hardware overhead.

We present a realization of the transparent wave absorber effective for the use at V-band frequency. First, we propose a structure of the transparent wave absorber consisting of spacer (polycarbonate) and two transparent resistive sheet (polyethylene terephtalate deposited with Indium Tin Oxide) used as a reflection film and an absorption film. Second, a design chart for this type of wave absorber is shown. Third, a design method and manufacturing process of the transparent wave absorber are described particularly for V-band frequency. As a result, the measurement of reflection loss of the absorber indicate that a peak absorption of 32-38 dB is attained at a target frequency of 60 GHz.

A mobility management scheme that reduces signaling traffic load and connection setup time is a pivotal issue in designing future personal communication service (PCS) networks to satisfy Quality of Services requirements and use network resources efficiently. Particularly, required is scalable mobility management, to meet the explosive growth in number of users for the current second-generation wireless communication systems, and to materialize PCS concepts such as terminal, personal, and service mobility. Many mobility management schemes have been proposed for the reduction of signaling traffic. However, these schemes have not been sufficiently compared using a unified performance measure that is free of assumptions as to mobility model or database architecture. In this paper, we categorize the various mobility management schemes for advanced PCSs in distributed environments into four types and clarify the appropriate domain for each type. To do this, we settled on the number of signals at connection setup and location registration as a unified performance measure, since this value closely relates to connection setup time and network efficiency. We found two kinds of schemes with replicating and caching functions of user information that are extremely effective for reducing signaling load and hence connection setup time. These schemes are appropriate when the probability that a user is in his/her home area is relatively small or the connection setup rate is relatively high compared to the location registration rate. These are the most likely situations in the advanced PCS for global environments.

The increasing activity at millimeter wave frequency band and the growing demand for waveguide components to be applied for integrated circuit purpose have promoted the need for applying the field-theory-based approaches to the design procedure. In this paper, genetic algorithms (GA's) are applied to accurately design the iris-coupled waveguide filters based on network-boundary element method (NBEM). GA's model the natural selection and evolve towards the global optimum, thus avoid being trapped in local minima. Network-boundary element method, which combines boundary element method with network analysis method, derives the network parameters of the guided wave structures with less storage location and central processing unit time. Therefore, NBEM is a feasible and efficient field-theory-based approach for the GA optimization of waveguide filters. With NBEM performing the task of evaluating the performance of the filter designs optimized by the GA, rigorous and optimal designs of the waveguide filters are realized. The obtained analysis and optimization results are compared to a number of reference solutions to demonstrate the validity and accuracy of the proposed approach.

This paper proposes a top-down co-verification approach in the design of embedded systems composed of both hardware and software, for multimedia applications. In order to realize the optimized embedded system in cost, performance, power consumption and flexibility, hardware/software co-design becomes to be essential. In this top-down co-design flow, a target design is verified at three different levels: (1) algorithmic, (2) implementation, and (3) experimental. We have developed a methodology of top-down co-verification, which consists of the system level simulation at the algorithmic level, two type of co-simulations at the implementation level and the co-emulation at the experimental level. We have realized an environment optimized for verification performance by employing verification models appropriate to each verification stage and an efficient top-down environment by introducing the component logical bus architecture as the interface between hardware and software. Through actual application to a image compression and expansion system, the possibility of efficient co-verification was demonstrated.

This paper proposes polling-based real-time software for MPEG2 System protocol LSIs, which is a typical embedded and real-time system on a chip, and demonstrates its performance and usefulness. The polling-based real-time software is designed and optimized by analyzing application specific function requirements and deciding scheduling intervals and the execution cycles of each task. It requires neither hardware for multiple interrupt handling nor software for heavy context switching. The polling-based approach provides sufficient performance without any hardware and software overhead for a real-time application like the MPEG2 System protocol.

This paper proposes a new method to improve cooperation in concurrent systems within the framework of Multi-Agent Systems (MAS). Since subsystems work concurrently, achieving appropriate cooperation among them is important to improve the effectiveness of the overall system. When subsystems are modeled as agents, it is easy to explicitly deal with the interactions among them since they can be modeled naturally as communication among agents with intended information. Contrary to previous approaches which provided the syntax of communication protocols without semantics, we focus on the semantics of cooperation in MAS and aim at allowing agents to exploit the communicated information for cooperation. This is attempted by utilizing more coarse-grained communication based on the different perspective for the balance between formality and richness of communication contents so that each piece of communication contents can convey more meaningful information in application domains. In our approach agents cooperate each other by giving feedbacks based on the metaphor of explanation which is widely used in human interactions, in contrast to previous approaches which use direct orders given by the leader based on the pre-defined cooperation strategies. Agents show the difference between the proposal and counter-proposals for it, which are constructed with respect to the former and given as the feedbacks in the easily understandable terms for the receiver. From the comparison of proposals agents retrieve the information on which parts are agreed and disagreed by the relevant agents, and reflect the analysis in their following behavior. Furthermore, communication contents are annotated by agents to indicate the degree of importance in decision making for them, which contributes to making explanations or feedbacks more understandable. Our cooperation method was examined through experiments on the design of micro satellites and the result showed that it was effective to some extent to facilitate cooperation among agents.

VP Network Designer, a software tool that automates the tasks involved in the transaction of service orders in VP leased line services, is introduced here in this paper. The tool is composed of two functions: VP Design Explorer which, given a request for VP establishment, determines a disjoint backup and target VP routes to support fault tolerance under VP-APS scheme; Network Resource Administrator which provides data administering functions, useful in maintaining a clear insight into the state of the network. The paper focuses on the implementation of VP Design Explorer. A scheme, proposed as disjoint VP routes search, is used to evaluate a pair of VP routes that guarantee duct level independence. The scheme is based on an integer programming modeling approach, and is proved to be effective for evaluating disjoint paths in a hierarchical network. VP Design Explorer is equipped with an additional feature where, under conditions of resource shortage, it presents a set of additional resources that are necessary to satisfy VP demand, together with the VP routes that become possible by the additions. Formulation of the problem is attained through an extension of the disjoint VP routes search scheme. A prototype of VP Network Designer is presented and its performance tested using computer simulations. The tool is found to achieve a computational time performance in the order of seconds and minutes, for evaluating disjoint VP routes search problems under real life ATM network conditions.

If the fiber dispersion of soliton transmission line is optimized, the amplifiers output power becomes almost constant for different amplifier spacing and pulse width. Numerical simulations indicate the optimal dispersion can be determined, as the ratio of amplifier spacing to dispersion length is about 0. 8 for uniform dispersion line.