In this paper, two distinct optical network design approaches, namely mesh and multi-ring, for survivable WDM networks are investigated. The main objective is to compare these two design approaches in terms of network costs so that their merits in practical environments can be identified. In the mesh network design, a new mathematical model based on integer liner programming (ILP) and a heuristic algorithm are presented for achieving a minimal cost network design. In the multi-ring network design, a heuristic algorithm that can be applied to large network problems is proposed. The influence of wavelength conversion and the number of wavelengths multiplexed in a fiber on system designs are also discussed. Based on the simulation results, the redundancy quantities required for full protection in multi-ring approach are significantly larger in comparison to the minimal cost mesh counterpart.

The forwarding speed of IP routers must grow to accommodate the skyrocketing amount of traffic on the Internet. MPLS, which relies on the high processing power of lower layers, is a solution and it is under developing. On the other hand, a WDM network has been expected as a high-speed network, but it is also called a stupid network because of lacking its traffic granularity. In order to bridge between these two layers, an IP over WDM network by a concept of MPLS has been proposed. This network has a potential to effectively use large transmission capacity provided by WDM technology. In this paper, we design IP over WDM networks that reconfigure IP routing and lightpaths each day or month. We formulate a problem that maximizes the network throughput based on integer linear programming. Through numerical examples, we show that the increase of the network throughput in IP over WDM networks is larger than that of IP networks. We also show the area where this method is applicable to the reconfigurable network.

The problem of self-timed implementation of Boolean functions is explained. The notions of combinational delay-insensitive code and delay-insensitive function are defined, giving precise conditions under which memoryless self-timed implementation of Boolean functions is feasible. Examples of combinational delay-insensitive code and delay-insensitive function are given. Generic design style, using standard CAD library, for constructing quasi delay-insensitive self-timed function blocks is suggested. Our design style is compared to other self-timed function block design styles.

In this paper, we consider the design for testability of a multiplier based on the modified Booth Algorithm. First, we present a basic array implementation of the multiplier. Next, we introduce testability considerations to derive two C-testable designs. The first of the designs is C-testable under the single stuck-at fault model (SAF) with 10 test patterns. And, the second is C-testable under the cell fault model (CFM) with 33 test patterns.

This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG), and its application to the design of fast constant-coefficient multipliers using parallel counter-tree architecture. An important feature of EGG is its capability to handle the general graph structures directly in evolution process instead of encoding the graph structures into indirect representations, such as bit strings and trees. This paper also addresses the major problem of EGG regarding the significant computation time required for verifying the function of generated circuits. To solve this problem, a new functional verification technique for arithmetic circuits is proposed. It is demonstrated that the EGG system can create efficient multiplier structures which are comparable or superior to the known conventional designs.

Most of current codesign tools or methodologies only support validation in the form of cosimulation and testing of design alternatives. The results of hardware-software codesign of a distributed system are often not verified, because they are not easily verifiable. In this paper, we propose a new formal coverification approach based on linear hybrid automata, and an algorithm for automatically converting codesign results to the linear hybrid automata framework. Our coverification approach allows automatic verification of real-time constraints such as hard deadlines. Another advantage is that the proposed approach is suitable for verifying distributed systems with arbitrary communication patterns and system architecture. The feasibility of our approach is demonstrated through several application examples. The proposed approach has also been successfully used in verifying deadline violations when there are inter-task communications between tasks with different period lengths.

This paper describes the formula for dynamic power dissipation of a track/hold circuit as a function of the input frequency, the input amplitude, the sampling frequency, the track/hold duty cycle, the power supply voltage and the hold capacitance for a sinusoidal input.

We propose a novel Bragg grating filter synthesis method using a Fourier transform of the target scattering matrix. Multiple scattering processes are taken into account by iteration to improve the synthesis accuracy.

Design patterns which Erich Gamma advocates is expected as an effective approach for the reuse of designs. So, design patterns are predicted to be used frequently in object-oriented software development. In such circumstance, tools to support applying design patterns to the design diagrams of the system under development are thought to be useful. This research develops Object-Oriented Pattern Applying Support tool OOPAS. It consists of a library of Gamma design patterns with very familiar examples and adrem explanation, and of a function to generate the correctly modified design diagrams of the application system when a design pattern was applied to evolve that system. Actually, these functions are installed in the structured object modeling environment SOME, which is an object-oriented design diagram editor made previously in our laboratory. This design diagram evolving function is formalized as a Join operation of the recursive graph. As a result of the evaluation experiment, the join operation can be applied to the almost of the twenty three Gamma design patterns excluding the six patterns such as Iterator and Command, which are stated at too abstract level to be represented by the design diagrams.

In this paper, a new frequency transformation for complex analog filter design which is suitable for integration is discussed. Arbitrary specified passband and stopband edges are easily transformed into those of the normalized LPF by solving simultaneous equations with four unknowns. Different from previous methods, the proposed transformation provides better performance in active realization of complex filters.

This paper presents a new design for testing SRAM-based field programmable gate arrays (FPGAs). The original FPGA's SRAM memory is modified so that the FPGA may have the facility to loop the testing configuration data inside the chip. The full testing of the FPGA is achieved by loading typically only one carefully chosen testing configuration data instead of the whole configurations data. The other required configurations data are obtained by shifting the first one inside the chip. As a result, the test becomes faster. This method does not need a large off-chip memory for the test. The evaluation results prove that this method is very effective when the complexity of the configurable blocks (CLBs) or the chip size increases.

This paper presents a novel technique for analyzing and designing local communication systems for distributed mobile robotic systems (DMRS). Our goal is to provide an analysis-base guideline for designing local communication systems to efficiently transmit task information to the appropriate robots. In this paper, we propose a layered methodology, i. e. , design from spatial and temporal aspects based on analysis of information diffusion by local communication between robots. The task environment is classified so that each analysis and design is applied in a systematic way. The spatial design gives the optimal communication area for minimizing transmission time for various cooperative tasks. In the temporal design, we derive the information announcing time to avoid excessive information diffusion. The designed local communication is evaluated in comparison with global communication. Finally, we performed simulations and experiments to demonstrate that the analysis and design technique is effective for constructing an efficient local communication system.

In this paper, a program generator for communication protocol software will be presented. Our program generator takes an extended finite state machine as a domain model and generates a group of C++ classes needed for an implementation. For each state of the FSM, a C++ class is generated, where the interface events are implemented as member functions of the corresponding state object. Protocol data units (PDUs) are embedded as Message objects and specified in the same way as packet filter and is interpreted to generate necessary PDU definition statements and PDU manipulation statements. Also, protocol objects from different layers can be linked together by using an organization model, where a protocol entity is invoked by its upper layer entity or lower layer entity by member function calls.

Packet concentrators are used in many high-speed computer communication systems such as fast packet switches. In these systems, the time available for concentration is very short. It is therefore desirable to realize the packet concentrators as hardware chips for fast concentration. The knockout concentrator was proposed for hardware realization. In this paper, we improve this concentrator to reduce the probability of packet loss, and the improved concentrator is called wraparound knockout concentrator. This concentrator has several wraparound paths within it, and it does not require any additional pin per chip. After contention among the packets in a slot, each winner goes to a distinct output, some losers circulate along the wraparound paths for contention in the subsequent slot, and the remaining losers are discarded. In this manner, some losers are not discarded immediately and they still have the chance to go to the outputs in the subsequent slot, thereby reducing the probability of packet loss. We analyze the number of logic gates required and the probability of packet loss. The numerical results show that if the proposed concentrator has a few wraparound paths, the probability of packet loss can already be reduced by orders of magnitude.

Formal description techniques (FDTs) such as VDM, Z, LOTOS, etc are powerful to develop safety-critical systems since they have strict semantics and mathematical reasoning basis. However, they have no methods or guides how to construct specifications unlike specification and design methods such as Object-Oriented Modeling and Technique (OMT), and that makes it difficult for practitioners to compose formal specifications. One of the solutions is to connect formal description techniques with some existing methods. This paper discusses a technique how to integrate FDTs with specification and design methods such as OMT so that we can have new methods to support writing formal specifications. The integration mechanism is based on transformation rules of specification documents produced following methods into the descriptions written in formal description techniques. The transformation rules specify the correspondences on two meta models; of methods and of formal description techniques, and are described as graph rewriting rules. As an example, we pick up OMT as a method and LOTOS as a FDT and define the transformation rule on their meta models.

To bridge a wide gap between the end users and the requirements engineers, we propose a business flow diagram for acquiring users' requirements of the object oriented software development in the business application domain. Each field of this diagram shows either a role or a responsibility of a particular person or an organization. This paper proposes a development method that the engineers acquire the requirements by using our diagrams. We have implemented a supporting tool based on this study for collaborating the requirements engineers with their users. At first, the end users of an information system to be developed draw diagrams representing the flows of information and physical objects in their work from their own points of view. Sometimes the engineers write them with the users. If all users submit their diagrams, then our tool collects them and constructs a total diagram. The requirements engineers analyze the total diagram for improving the business flow. After the engineers complete this diagram, our tool can automatically transform it into an initial version of the class diagram. We show the effectiveness of our approach with some experiments. Comparing the related works, we discuss some issues of the practical aspects of this proposal.

This paper discusses the characteristics of human design knowledge. By studying a number of actual human made designs of excellent designers, the most frequent basic mental operations of a typical human designer have been found. They are: a design rule for hierarchical detailing reported previously, a micro design rule for generating a hierarchical expansion, dictionary operations to build a micro design rule and dictionaries. This study assumes a multiplicity of knowledge based on Zipf's theory, "the principle of least effort. " Zipf's principle may be proved and it becomes possible to understand the fundamental nature of human design.

This paper presents an architecture for a single-chip MPEG-2 video encoder and demonstrates its flexibility and usefulness. The architecture based on three-layer cooperation provides flexible data-transfer that improves the encoder from the standpoints of versatility, scalability, and video quality. The LSI was successfully fabricated in the 0.25-µm four-metal CMOS process. Its small size and its low power consumption make it ideal for a wide range of applications, such as DVD recorders, PC-card encoders and HDTV encoders.

Low Power design has emerged as a both practically and theoretically attractive theme in modern LSI system design. This paper presents system level power optimization techniques. A brief survey of system level low power design approaches and several examples in detail are described. It reviews some techniques that have been proposed to overcome the power issue and gives guideline for prospective system level solutions.

This paper reviews design aspects of computational discovery systems through the analysis of some successful discovery systems. We first review the concept of viewscope/view on data which provides an interpretation of raw data in a specific domain. Then we relate this concept to the KDD process described by Fayyad et al. (1996) and the developer's role in computational discovery due to Langley (1998). We emphasize that integration of human experts and discovery systems is a crucial problem in designing discovery systems and claim together with the analysis of discovery systems that the concept of viewscope/view gives a way for approaching this problem.