This paper presents a Path Bandwidth Management (PBM) model for large-scale networks that leads to an almost optimal PB allocation, under constraints posed by the installed bandwidth in the transmission links of the network. The PB allocation procedure is driven from a traffic demand matrix and consists of three phases. In the first phase, a suitable decomposition of the whole network takes place, where the large-scale network is split to a set of one-level sub-networks. In the second phase, the optimization algorithm developed for one-level telecommunication networks is applied to each sub-network in order to define the optimal PB allocation. The criterion for optimization is to minimize the worst Call Blocking Probability (CBP) of all switching pairs of the sub-network. In the third phase, composition of the sub-networks takes place in a successive way, which leads to the final PB allocation of the large-scale network. As the large-scale network is built up from optimized sub-networks, an almost optimal PB allocation is anticipated. For evaluation, the worst resultant CBP of the proposed scheme is compared with that obtained by the optimal PB allocation procedure in order to prove its optimality and efficiency. We choose a set of large-scale networks whose size is not very large so that we can apply the optimization algorithm developed for one-level telecom networks for defining its optimal bandwidth allocation. Extensive evaluation of the PBM model has showed that the worst resultant CBP is about 2% above the optimal value, which is a satisfactory result. The proposed PBM scheme is explained by means of an application example.

This paper proposes a novel cache architecture suitable for merged DRAM/logic LSIs, which is called "dynamically variable line-size cache (D-VLS cache). " The D-VLS cache can optimize its line-size according to the characteristic of programs, and attempts to improve the performance by exploiting the high on-chip memory bandwidth on merged DRAM/logic LSIs appropriately. In our evaluation, it is observed that an average memory-access time improvement achieved by a direct-mapped D-VLS cache is about 20% compared to a conventional direct-mapped cache with fixed 32-byte lines. This performance improvement is better than that of a doubled-size conventional direct-mapped cache.

Reverse link performance analysis in single-code and multi-code CDMA systems is presented. Results show that the single-code system yields better performance than does the multi-code system in terms of link capacity and signal power. This improvement increases as spreading bandwidth is reduced and the number of spreading codes assigned to a user is increased.

The Virtual Path (VP) concept in ATM networks simplifies network structure, traffic control and resource management. For VP formulation, a VP can carry traffic of the same type (the separate scheme) or of different types (the unified scheme). For VP adjustment, a certain amount of bandwidth can be dynamically assigned (reserved) to VPs, where the amount (the bandwidth incremental/decremental size) is a predetermined system parameter. In this paper, we study Least Loaded Path-based dynamic routing schemes with various residual bandwidth definitions under different bandwidth allocation (VP formulation and adjustment) schemes. In particular, we evaluate the call blocking probability and VP set-up processing load with varying (bandwidth) incremental sizes. Also, We investigate numerically how the use of VP trades the blocking probability with the processing load. It is found that the unified scheme could outperform the separate scheme in certain incremental sizes. Moreover, we propose two ways to reduce the processing load without increasing the blocking probability. Using these methods, the separate scheme always outperforms the unified scheme.

This paper proposes a new self-healing scheme that differentiates the bandwidth requirement for each network service on ATM networks. First, we show the necessity of our proposed scheme. In the future network, we must satisfy two demands, rapid restoration from failure and differentiated bandwidth requirements. The conventional restoration scheme, called the self-healing scheme, realizes rapid restoration, but does not support bandwidth differentiation; the new self-healing scheme proposed herein does. We also show that the proposed scheme reduces the spare resources required for backup. The scheme can be realized as a simple extension of the conventional self-healing scheme. Finally, simulations show that the proposed scheme requires fewer spare resources while offering comparable restoration time to the conventional approach against any demand pattern.

We compare between four Connection Admission Control schemes that use either the Gaussian or the Effective Bandwidth model with and without real-time traffic measurements. We demonstrate that under heavy multiplexing, the Gaussian is more efficient than the Effective Bandwidth approach in either case.

Increasing traffic on the Internet and intranets has raised demands for high-speed, large-scale and cost-effective computer networking techniques. ATM connectionless service provides high-speed, highly scalable, and flexible services because connectionless networks are constructed logically over high-speed ATM networks. This paper described the self-sizing operation for high-speed, large-scale connectionless service over an ATM network. Self-sizing is an autonomous adjustment mechanism for virtual path (VP) bandwidths based on traffic conditions observed in real time. We confirmed its feasibility on a test-bed network. The self-sizing operation caused the VP bandwidth to approach the necessary value while satisfying the target cell loss ratio (CLR). We developed an operations system (OpS) that achieves self-sizing in an ATM connectionless network. The OpS suggests necessary bandwidth for VP that may exceed the target CLR. The algorithm utilized in the OpS does not require observation or logical processes, which would be a heavy load on each node. Self-sizing operation will provide easy and cost-effective management because it adjusts VP bandwidth flexibly depending on the current traffic demand.

The VSOP terminal is a new data-acquisition system for the Very-Long-Baseline Interferometry (VLBI). This terminal was primarily designed for ground telescopes in the VLBI Space Observatory Programme (VSOP). New technologies; higher-order sampling and digital filtering techniques, were introduced in the development. A cassette cart was also introduced, which supports 24-hour unattended operations at the maximum data rate of 256 Mbps. The higher-order sampling and digital filtering techniques achieve flat and constant phase response over bandwidth of 32 MHz without using expensive wide base-band converters. The digital filtering technique also enables a variety of observing modes defined on the VSOP terminal, even with a fixed sampling frequency in an A/D converter. The new terminals are installed at Nobeyama, Kashima, Usuda, Mizusawa, and Kagoshima radio observatories in Japan, and are being used in VSOP and other domestic VLBI observations. In this paper the key features of the VSOP terminal focusing on these advanced technologies are presented, and the results of performance tests are shown.

The performance of TCP/IP over ATM over an asymmetric digital subscriber line (ADSL) was investigated. Because the bandwidth of an ADSL link can vary over time due to changes in the link's physical conditions, which degrades TCP performance, we performed simulations for various ATM traffic controls, including available bit rate (ABR) and generic flow control, used to handle variations in the ADSL bandwidth. This analysis showed that using an ABR control is effective under various traffic conditions. An ABR switch algorithm that can achieve good performance under any condition was investigated.

Various kinds of high bandwidth architecture using the embedded DRAM technology have been presented previously. In most cases, they use wide bus implementation and/or fast bus speed, that both have the penalty of die area and much power consumption at the same time. The proposing single-ended read-modify-write bus increases the bandwidth twice as high, while it maintains the same bus size and the same bus speed. The data-bus comprises 1 k-bit read-bus and 1 k-bit write-bus that each works concurrently, and has amplitude from 0 V to 1 V, hence the measured power consumption is only 0.3 W at a frequency of 166 MHz. A programmable page-size reduces the page miss-rate and efficiently improves the bandwidth that is comparable to the wide bus and fast speed approach. All the proposing features are implemented on a 3D frame-buffer to achieve 42.4 G-BPS bandwidth.

This paper addresses an important issue on the spreading bandwidth of direct sequence code division multiple access (DS-CDMA) cellular mobile radio systems: does wider spreading bandwidth provide larger capacity? And if so, to what extent? The capacity of the perfect power controlled reverse link is evaluated by computer simulation for 1.25 MHz and 5 MHz spreading bandwidths under various sets of propagation channel parameters (path loss decay factor, shadowing standard deviation, shadowing correlation, number of resolved propagation paths) and antenna diversity reception.

Linear signal analysis (LSA) is the conventional method of estimating the playback voltage and pulse width in linearly operating shielded GMR heads. To improve the accuracy of LSA, a new, highly precise LSA which includes the effect of the magnetization distribution in the medium and inhomogeneous biasing by domain control magnets, was developed. Utilizing this new LSA to calculate the playback waveforms, the calculated peak voltage and pulse width were compared with the experimental values and agreement within 10% was obtained. As the result of estimation using the new LSA, it is considered that the use of a vertical-type spin-valve head will make it possible to achieve a recording areal density of 40 Gb/in2.

A fully on-chip current controlled open-drain output driver using a bandgap reference current generator was designed for high bandwidth DRAMs. It reduces the overhead of receiving a digital code from an external source for the compensation of the temperature and supply voltage variations. The correct value of the current control register is updated at the end of every auto refresh cycle. The operation at the data rate up to 0.8 Gb/s was verified by SPICE simulation using a 0.22 µm triple-well CMOS technology.

This paper proposes non-volatile analog memory circuits using pulse-width modulation (PWM) methods. The conventional analog memory using floating gate device has a trade-off between programming speed and precision because of the constant width of write pulses. The proposed circuits attain high programming speed with high precision by using PWM write pulses. Three circuits are proposed and their performance is evaluated using SPICE simulation. The simulation results show that fast programming time less than 20 µs, high updating resolution of 11 bits, and high precision more than 7 bits are achieved.

This letter proposes a diffusion model that considers both mobility and multimedia based on the user population process to examine the effects of multimedia in mobile communications. As an application example of this model, the shared bandwidth that can be used by one user in packet communications is evaluated. In this model, the user speed and variation in the number of users in a cell are interrelated with respect to mobility. By examining the shared bandwidth behavior based on multimedia teletraffic characteristics, assuming that the number of simultaneously-communicating users within a cell have self-similarity, we found that shared bandwidth and its variance are not dependent on self-similarity but that variance in the shared bandwidth is dependent on user speed.

We propose a novel planar filter design for narrow-band applications. The filter consists of half-wavelength ring resonators with open gaps. This design has three advantages over conventional planar designs: a smaller size despite narrow bandwidth, a sharper skirt response at the passband edge without notch, an excellent out-band attenuation. We demonstrated these advantages by fabricating an 8-poles filter centered at 1.95 GHz with a 5 MHz bandwidth using YBCO films on a 2 inch diameter MgO substrate.

Even though information in ATM networks is handled as fixed-sized packets (cells), packet-based scheduling is still needed in ATM networks. This letter proposes a packet-based scheduling mechanism that is based on comparison between a packet-based queue and a virtual queue that represents the queue length provided by a cell-based scheduling mechanism. Simulation results showed that this proposed scheduling allocates the bandwidth fairly to each connection.

The ATM Forum specifies several fairness criteria, thus the scheduling mechanisms should allocate enough bandwidth to each connection to achieve one of such fairness criteria. However, two fairness criteria (MCR plus equal share, maximum of MCR or Max-Min share) cannot be achieved by conventional scheduling mechanisms. In this letter, we have developed new scheduling mechanisms that achieve these fairness criteria. We also present simulation results to show that our mechanisms can allocate bandwidth fairly.

This paper reports on the use of microelectronic test structures to characterise a novel fabrication technique for thin-film electronic circuit boards. In this technology circuit tracks are formed on paper-like substrates by depositing films of a metal-loaded ink via a standard lithographic printing process. Sheet resistance and linewidth for both horizontal and vertical lines are electrically evaluated and these compared with optical and surface profiling measurements.

This paper presents a high-speed CAC scheme, called PERB CAC (CAC based on Prior Estimation for Residual Bandwidth). This scheme estimates the residual bandwidth in advance by generating virtual requests for connection. When an actual new request occurs, PERB CAC can instantaneously judge if the required bandwidth is larger than the estimated residual bandwidth. PERB CAC provides very rapid response time both for statistical and deterministic bandwidth allocation services, while keeping statistical multiplexing gain for the former service. Numerical results indicate that PERB CAC provides reasonably accurate and conservative values of residual bandwidth. In addition, by using PERB CAC, both services are able to be accommodated into a single VP. VP capacity control is more relaxed than is true with conventional VP-separation management. This is another merit of PERB CAC. Therefore, PERB CAC can achieve high-speed connection set-up while utilizing network resources in a cost-effective manner.