A design methodology of the analog currentmode bandwidth programmable integrator for a low voltage (3V) and low power application is developed and the integrator designed by this method is successfully fabricated by a 0.8µm CMOS n-well single poly/double metal process. The integrator ocuppies the active chip area of 0.3mm2. The experimental result illustrates a low power dissipation (1.0mW-3.55mW), 65dB of the dynamic range, and bandwidth programmability (10MHz-30MHz) with an external digital 4bit.

This paper presents a salient method to find an optimal bandwidth for low noise phase-locked loop (PLL) applications by analyzing a discrete-time model of charge-pump PLLs based on ring oscillator VCOs. The analysis shows that the timing jitter of the PLL system depends on the jitter in the ring oscillator and an accumulation factor which is inversely proportional to the bandwidth of the PLL. Further analysis shows that the timing jitter of the PLL system, however, proportionally depends on the bandwidth of the PLL when an external jitter source is applied. The analysis of the PLL timing jitter of both cases gives the clue to the optimal bandwidth design for low noise PLL applications, Simulation results using a C-language PLL model are compared with the theoretical predictions and show good agreement.

Ordered Binary Decision Diagrams (OBDDs) are graph-based representations of Boolean functions which are widely used because of their good properties. In this paper, we introduce nondeterministic OBDDs (NOBDDs) and their restricted forms, and evaluate their expressive power. In some applications of OBDDs, canonicity, which is one of the good properties of OBDDs, is not necessary. In such cases, we can reduce the required amount of storage by using OBDDs in some non-canonical form. A class of NOBDDs can be used as a non-canonical form of OBDDs. In this paper, we focus on two particular methods which can be regarded as using restricted forms of NOBDDs. Our aim is to show how the size of OBDDs can be reduced in such forms from theoretical point of view. Firstly, we consider a method to solve satisfiability problem of combinational circuits using the structure of circuits as a key to reduce the NOBDD size. We show that the NOBDD size is related to the cutwidth of circuits. Secondly, we analyze methods that use OBDDs to represent Boolean functions as sets of product terms. We show that the class of functions treated feasibly in this representation strictly contains that in OBDDs and contained by that in NOBDDs.

In this paper, we introduce a VP rearrangement scheme to realize the dynamic control of ATM network. We demonstrate its effectiveness for the transport of B-ISDN traffic which is both fluctuous and hard to predict. First, we present a strategy for the ATM network provisioning, used to manage both the logical VP network and the underlying physical transport network. We then propose a VP rearrangement scheme and discuss its performance. Lastly, we analyze the proposed scheme by simulations, and confirm that its performance, in comparison to the conventional, dynamic VP bandwidth control scheme, is superior.

This paper discusses the problems in designing virtual-path (VP) networks and underlying transmission-path (TP) networks using the "self-sizing" capability. Self-sizing implies an autonomous adjustment mechanism for VP bandwidths based on traffic conditions observed in real time. The notion of "bandwidth demand" has been introduced to overcome some of the problems with VP bandwidth sizing, e.g., complex traffic statistics and diverse quality of service requirements. Using the bandwidth demand concept, a VP-bandwidth-sizing procedure is proposed in which real-time estimates of VP bandwidth demand and successive VP bandwidth allocation are jointly utilized. Next, TP bandwidth demand, including extra capacity to cover single-link failures, is defined and used to measure the congestion level of the TP. Finally, a TP provisioning method is proposed that uses TP "lifetime" analysis.

As the demand for communications via satellite is rapidly increasing, techniques that produce large traffic capacity are becoming more and more appreciated. We present a class of block coded modulation (BCM) and multiple block coded modulation (MBCM) schemes in this paper. While the BCM scheme is directly derived from our previous work, the MBCM schemes are newly developed using a technique of multiple symbol transmission via a single trellis branch. This class of BCM and MBCM schemes is both power and bandwidth efficient. They also have an advantage in holding both a trellis and a block structure. Code structures, decoding trellises and the corresponding branch variables of these BCM and MBCM schemes are all derived. Their applications to satellite communications are discussed. Computer simulations are performed to verify coding gain performance.

A new simple cell spacing architecture that guarantees the peak cell interval and realizes preferential contention resolution is proposed. Scheduling the cell emission on departure of the previous cell, not arrival, allows the source peak cell interval to be regenerated without clumping. Priority control is also realized in the proposed spacer. A connection is scheduled either at the head or tail of the contention chain depending on its priority. The proposed method is applied to realize the UPC function. The proposed cell spacer eliminates the clumping effects of CDV completely and achieves high bandwidth efficiency.

It has been known that an N-vertex binary tree can be embedded into the path and grid with dilation O(N/logN) and O((N/logN)), respectively. This paper shows that an N-vertex binary tree with proper pathwidth at most k can be embedded into the path grid with dilation O(N/N1/k) and O((N/N1/2k)), respectively.

This paper presents an improved pragmatic approach to coded modulation design which provides higher coding gains especially for very noisy channels including those with Rayleigh fading. The signal constellation using four equally utilized dimensions implemented with two correlative carrier frequencies is adopted to enhance the performance of the pragmatic approach previously proposed by Viterbi et al.. The proposed scheme is shown to perform much better by analysis of system performance parameters and extensive computer simulation for practical channel conditions. The bandwidth and power efficiencies are also analyzed and discussed to provide more design flexibility for different communications environments.

We propose the Kernel MUSIC algorithm as an improvement over the conventional MUSIC algorithm. This algorithm is based on the orthogonality between the image and kernel space of an Hermitian mapping constructed from the received data. Spatial smoothing, needed to apply the MUSIC algorithm to coherent signals, is interpreted as constructing procedure of the Hermitian mapping into the subspace spanned by the constituent vectors of the received data. We also propose a new spatial smoothing technique which can remove the redundancy included in the image space of the mapping and discuss that the removal of redundancy is essential for improvement of resolution. By computer simulation, we show advantages of the Kernel MUSIC algorithm over the conventional one, that is, the reduction of processing time and improvement of resolution. Finally, we apply the Kernel MUSIC algorithm to the Laser Microvision, an optical misroscope we are developing, and verify that this algorithm has about two times higher resolution than that of the Fourier transform method.

This paper presents the system issues involved with the transmission of pre-encoded VBR MPEG video using CBR service. Conventional wisdom suggests that lossless delivery of VBR video using CBR service requires bandwidth to be reserved at the peak rate resulting in low bandwidth utilization. We calculate the minimum rate at which bandwidth must be reserved on a network in order to provide continuous playback of an MPEG encoded video bitstream. Simulation results using the frame size traces from several pre-encoded MPEG bitstreams and several buffer sizes demonstrate that this minimum reservation rateis much lower than the peak rate when a relatively small playback buffer size is used, resulting in much higher bandwidth utilization. Procedures for performing connection setup and lossless realtime video playback between the video server and the client are outlined. Methods for incorporating VCR-like features such as pauseandfast forward/reversefor Video-on-Demand (VoD) applications are presented.

This paper is concerned with bandwidth reservation for circuit groups which handle calls requesting asymmetric forward and backward multi-connections. A model of circuit group with sub-group configuration is treated, and two types of the bandwidth reservation schemes for the model are studied in this paper. One is a global scheme with monitoring the whole circuit group, and the other is a local scheme with monitoring each sub-group independently. The problems of optimizing the reservation parameters are formulated, and optimization methods for the problems are proposed. Numerical example are presented, and effectiveness of the reservation schemes with using the optimized parameters is numerically examined.

We propose burst based bandwidth reservation method called FRP (Fast Reservation Protocol) in ATM LAN with general topology, and evaluate its performance. In FRP, the bandwidth is allocated on each link on burst basis, not on call basis. This enables an effective use of network resources when it is applied to highly bursty traffic, which can be typically found in data communications. The problem of FRP is that VCs traversing the different number of links experience different blocking probabilities as can be found in the conventional circuit-switching networks. In this paper, we treat a fairness issue in FRP-based ATM local area networks. The Max-Min flow control is adopted as the fair bandwidth allocation method to accomplish the fairness in the throughput. However, the original Max-Min flow control works in a centralized fashion, which is not desirable in the FRP-based ATM LAN. We therefore propose a "semi"-distributed Max-Min flow control suitable to FRP, in which each switch maintains its own local information about bandwidth usage of the connected links. Through simulation experiments, we show that the proposed semi-distributed Max-Min flow control can achieve the fairness among VCs as the original Max-Min flow control when the propagation delays are not large and the number of VCs is not so much.

Various kinds of new architectures have been proposed to enhance operating performance of the DRAM. This paper reviews these architectures including EDO, SDRAM, RDRAM, EDRAM, and CDRAM. The EDO slightly modifies the output control of the conventional DRAM architecture. Other innovative architectures try to enhance the performance by taking advantage of DRAM's internal multiple bits architecture with internal pipeline, parallel-serial conversion, or static buffers/on-chip cache. A quantitative analysis based on an assumption of wait cycles was made to compare PC system performance with some architectures. The calculation indicated the effectiveness of external or on-chip cache. Future trends cover high-speed I/O interface, unified memory architecture, and system integrated memory. The interface includes limited I/O swing such as HSTL and SSTL to realize more than 100MHz operation. Also, Ramlink and SyncLink are briefly reviewed as candidates for next generation interface. Unified memory architecture attempts to save total memory capacity by combining graphics and main memory. Advanced device technology enables system integration which combine system logic and memory. It suggests one potential direction towards system on a chip in the future.

A new electron-beam wafer inspection system has been developed. The system has a resolution of 5 nm or better, and is applicable to quarter-micron devices such as 256 Mbit DRAMs. The most remarkable feature of this system is that a specimen stage is built in the objective lens and allows a working distance (WD) of 0. "WD=0"minimizes the effect of lens aberrations, and maximizes the resolving power. Innovative designs to achieve WD=0 are as follows: (1)A large objective lens of 730-mm width 730-mm depth 620-mm height that serves as a specimen chamber, has been developed. (2)A hollow specimen stage made of non-magnetic materials has been developed.It allows the lower pole piece and magnetic coile of the objective lens inside it. (3)Acoustic motors made of non-magnetic materials are em-ployed for use in vacuum.

We propose a partitioned-bus architecture with a variable-width-bus scheme to reduce power consumption in bus lines in VLSIs. The partitioned-bus architecture (horizontal partitioning) restricts bus driving range to minimal, while the variable-width-bus scheme (vertical partitioning) uses additional tag lines so as to automatically indicate effective bus width with-out driving unnecessary bus lines depending on data to be transferred. Applying this method to a general purpose microprocessor, we demonstrate 30% and 35% power consumption reduction in bus lines, respectively for the partitioned-bus architecture and the variable-width-bus scheme, compared with the conventional bus architecture. Combining the both together, we show about 55% power consumption reduction in bus lines for typical applications. Increase in chip area for this architecture is about 30% compared with the conventional bus architecture.

This letter proposes a pulse width modulated (PWM) control method which can stabilize chaotic orbits onto unstable fixed points and unstable periodic orbits. Some numerical experiments using the Lorenz equation show that chaotic orbits can be stabilized by the PWM control method. Furthermore, we investigate the stability in the neighborhood of an unstable fixed point and discuss the stability condition of the PWM control method.

This paper describes the new analog-digital merged circuit architecture which utilizes the pulse modulation signals. By reconsidering the information representing and processing principles, and the circuit operations governed by the physical law, the new circuit architecture is proposed to overcome the limitations of existent VLSI technologies. The proposed architecture utilizes the pulse width modulation (PWM) signal which has analog information in the time domain, and be constructed with the novel PWM circuits which carry out the multi-input arithmetic operations, the signal conversions and the data storage. It has a potential to exploit the high speed switching capability of deep sub-µm devices, and to reduce the number of devices and the power dissipation to one-tenth of those of the binary digital circuits. Therefore it will effectively implement the intelligent processing systems utilizing 0.5-0.2µm scaled CMOS devices.

An ATM network design algorithm is treated as a resource allocation problem. As an effective way to facilitate a coexistence of traffic with its diverse characteristics and different quality of service (QOS) requirements in ATM networks, a virtual path (VP) concept has been proposed. In attempting to design the VP (Virtual Path)-based ATM network, it requires to consider a network topology and traffic pattern generated from users for minimizing a network construction cost while satisfying QOS requirements such as cell / call loss probabilities and cell delay times. In this paper, we propose a new heuristic design algorithm for the VP-based ATM network under QOS constraints. A minimum bandwidth required to transfer a given amount of traffic is first obtained by utilizing an equivalent bandwidth method. After all the routes of VPs are temporarily established by means of the shortest paths, we try to minimize the network cost through the alternation of VP route, the separation of a single VP into several VPs, and the introduction of VCX nodes. To evaluate our design algorithm, we consider two kinds of traffic; voice traffic as low speed service and still picture traffic as high speed service. Through numerical examples, we demonstrate that our design method can achieve an efficient use of network resources, which results in the cost-effective VP-based ATM network.

Effects of field edge steps on characteristics of MOSFETs with tungsten polycide stacked gate electrodes patterned by KrF excimer laser lithography was studied through an electrical gate length measurement technique. Sheet resistance of the gate electrodes on the field oxide, on the active region and across the field edge steps was determined from the relationship between gate conductance and designed gate linewidth. The sheet resistance of the gate electrode across the field edge steps was larger than that on the flat regions. Effects of field edge steps on gate linewidth variation were evaluated by SEM observations and electrical measurements. Distribution of gate linewidth in a wafer was measured by the MOSFET test structures with the linewidth down to sub-quarter micron. Gate linewidth variation near the field edge steps was found to influence the short channel MOSFET characteristics.