Recent work in the area of ultrafast optical time-division multiplexed (OTDM) networking at MIT Lincoln Laboratory is presented. A scalable helical local area network or HLAN architecture, presented elsewhere as an architecture well-suited to ultrafast OTDM LANs and MANs, is considered in the context of wide area networking. Two issues arise in scaling HLAN to the wide area. The first is protocol extension, and the second is supporting the required bandwidth on the long-haul links. In this paper we discuss these challenges and describe progress made in both architecture and technologies required for scaling HLAN to the wide area.

This paper proposes a 3-stage ATM switch architecture that uses optical WDM (wavelength division multiplexing) grouped links and dynamic bandwidth sharing. The proposed architecture has two features. The first is the use of WDM technology which makes the number of cables used in the system proportional to system size. The second is the use of dynamic bandwidth sharing among WDM grouped links. This prevents the statistical multiplexing gain offered by WDM from falling even if switching system becomes large. A performance evaluation confirms the scaleability and cost-effectiveness of the proposed architecture. It is scaleable in terms of the number of cables and admissible load. We show how the appropriate wavelength signal speed can be determined to implement the switch in a cost-effective manner. Therefore, the proposed architecture will suit future high-speed multimedia ATM networks.

This paper presents a neural circuit using PWM technique based on an analog-digital merged circuit architecture. Some new PWM circuit techniques are proposed. A bipolar-weighted summation circuit is described which attains 8-bit precision in SPICE simulation at 5 V supply voltage by compensating parasitic capacitance effects. A high performance differential-type latch comparator which can discriminate 1 mV difference at 100 MHz in SPICE simulation is also described. Next, we present a prototype chip fabricated using a 0.6µm CMOS process. The measurement results demonstrate that the overall precision in the weighted summation and the sigmoidal transformation is 5 bits. A neural network has been constructed using the prototype chips, and the experimental results for realizing the XOR function have successfully verified the basic neural operation.

Recent work in the area of ultrafast optical time-division multiplexed (OTDM) networking at MIT Lincoln Laboratory is presented. A scalable helical local area network or HLAN architecture, presented elsewhere as an architecture well-suited to ultrafast OTDM LANs and MANs, is considered in the context of wide area networking. Two issues arise in scaling HLAN to the wide area. The first is protocol extension, and the second is supporting the required bandwidth on the long-haul links. In this paper we discuss these challenges and describe progress made in both architecture and technologies required for scaling HLAN to the wide area.

This paper proposes a 3-stage ATM switch architecture that uses optical WDM (wavelength division multiplexing) grouped links and dynamic bandwidth sharing. The proposed architecture has two features. The first is the use of WDM technology which makes the number of cables used in the system proportional to system size. The second is the use of dynamic bandwidth sharing among WDM grouped links. This prevents the statistical multiplexing gain offered by WDM from falling even if switching system becomes large. A performance evaluation confirms the scaleability and cost-effectiveness of the proposed architecture. It is scaleable in terms of the number of cables and admissible load. We show how the appropriate wavelength signal speed can be determined to implement the switch in a cost-effective manner. Therefore, the proposed architecture will suit future high-speed multimedia ATM networks.

Major problems of traffic control in ATM networks include how to decide whether a network accepts a new call or not in real time and how to select the best set of Dual Leaky Bucket (DLB) parameter values. To solve these problems, it is necessary to determine the amount of network bandwidth required by the call. In this paper, we present an analysis based on bounding technique to derive an upper bound on bandwidth requirement when the call is characterized by a set of DLB parameters. Consequently, a new definition of the upper bound on bandwidth requirement and simple formulae used for computing the upper bound have been obtained. To clarify the advantages of the derived upper bound, we demonstrate its two applications, one to select the best set of DLB parameter values from candidates for minimizing the amount of bandwidth to be allocated to the call and the other to establish a Connection Admission Control (CAC) scheme. The upper bound-based CAC scheme is fast enough to process in real time due to its simplicity and provides a significant improvement of network utilization compared to the peak rate-based CAC scheme.

The explosive increase of traffic in computer communications is a clear sign that we have entered the multimedia information age. To cope with this ever increasing need, economical optical access networks that support burst traffic such as in the Internet are expected to be developed. The ATM-PON is considered to be a promising candidate for such a network, and vigorous efforts in this direction are being promoted worldwide. This paper focuses on accommodating burst traffic in the ATM-PON. In order to do this, a mechanism to transport bandwidth requests from the ONU to the OLT and an algorithm to support dynamic bandwidth allocations based on ONU requests are needed. We have performed a comparative study on bandwidth request methods and bandwidth allocation algorithms, including bandwidth request dependence on time interval and correlation and/or impact between system design parameters. The results of computer simulations are useful in determining how to accommodate burst traffic efficiently in the ATM-PON.

A Pragmatic Trellis Coded MPSK on a Rayleigh fading channel is analyzed. This scheme allows bandwidth expansion ratio to be varied aiming at an optimization between complexity of the system design and improvement of coding gain. In order to vary the bandwidth expansion ratio, a punctured convolutional code is used. The performance of the proposed TC-2mPSK on a Rayleigh fading channel is theoretically analyzed. In the test examples, the BER performances of TC-QPSK and TC-8PSK are evaluated by theoretical analyses and computer simulations at the encoder parameters of K3 and r3/4. The results show that the proposed scheme can attain better performance not only over the uncoded scheme but over the conventional Pragmatic TCM.

In a multi-bandwidth CDMA system, the performance of a multiple order selection combining rake receiver is analyzed according to the spreading bandwidth of the system and the delay spread of a Rayleigh fading channel. The results for various channel environments indicate a tradeoff between total received signal energy and multipath fading immunity. Increasing the occupied bandwidth of the system (wide-bandwidth spreading) gives better performance for small delay spread environments, while gathering more energy (narrow-bandwidth spreading) gives better performance for large delay spread environments. It is also shown that the performance difference between low and high order selection combining grows larger as the spreading bandwidth is increased. It is noted that performance degrades by increasing the bandwidth above a certain point and the optimum spreading bandwidth for each channel environment decreases as the delay spread of the channel increases.

Priority control and call admission control are indispensable traffic management methods to guarantee each QoS requirement of connections in ATM networks. The key technique of call admission control under priority control is to estimate required bandwidth of each connection to satisfy all QoSs of calls in progress. In this paper, we propose a novel approximation method to calculate the required bandwidth of ATM connections through priority queues and show a practical call admission control scheme using the proposed method. The essence of the approximation method is to model prioritized parallel queues as a series of queues in tandem with no priority control by focusing on the number of cells in queues. The tandem queue approximation method enables us to model each queue under priority control as a single non-priority FIFO queue in terms of its queue length. This results in that effective bandwidth techniques are applicable to priority queues. The effectiveness of the proposed scheme is evaluated by some numerical examples.

In this paper, Orthogonal Multicode OFDM-DS/CDMA system using Partial Bandwidth Transmission is proposed. By using the flexible carrier allocation of OFDM, Partial Bandwidth Transmission is considered for high quality communication. Furthermore, multicode packet data transmission is presented. Multicode packet data transmission is very effective to handle variable data. Since the proposed system can detect the header information without complex control, it is also suitable for packet data transmission. The computer simulation results show that the BER performance of the proposed system with the ideal channel estimation is improved compared with the case of the conventional Orthogonal Multicode DS/CDMA system with ideal RAKE receivers. Moreover the proposed system with the channel estimation by MLS algorithm also shows the good BER performance. In packet data transmission, the delay and throughput performances are also improved in the proposed system.

In the design of an embedded system, an architecture of core processor strongly affects the performance and cost of the total system. This paper discusses a scalable processor architecture, called soft-core processor, which can be tuned for a target system. System designers can optimize several design parameters such as the datapath width and instruction set, and generate customized processors for their application. Design of Bung-DLX as a prototype of soft-core processor is presented in this paper. An experiment of system design using our processor has shown that the optimized processor chip area halves when the critical path delay is reduced to one third of the original one.

An important issue in accelerating the introduction of ATM networks is to offer more convenient access to the customer and a more efficient ATM system architecture. Regarding the first point, ATM network customers are currently inconvenienced by the need to declare traffic parameters, such as peak and average cell rates to the network provider before using the network. However, it is difficult for a customer to predict traffic parameters. This paper proposes a new ATM system with a dynamic bandwidth estimation and allocation scheme. This eliminates the need for traffic parameter declaration, and realizes more convenient ATM service. The proposed ATM system is a ring network. Bandwidth estimation is carried out by the "Network Server" located on the ring network. The estimation is achieved by observing the parameters closely related to media access control (MAC) protocols of LAN/MAN systems. Based on an estimation of customer traffic, the "Network Server" effectively allocates the bandwidth to each customer. This realizes a more efficient ATM network.

Media processors have emerged so that a single LSI can realize multiple multimedia functions, such as graphics, video, audio and telecommunication with effectively shared hardware and flexible software. First, the difference between media processors and general-purpose microprocessors with multimedia extensions is clarified. Features for processes and data in the multimedia applications are summarized and are followed by the multimedia enhancements that the recent general-purpose microprocessors use. The architecture for media processors reflects the further optimized utilization of these features and realizes better price-performance ratio than the general-purpose microprocessors. Finally, the future directions of media processors are estimated, based on the performance, the power dissipation and the die size of the present microprocessors with multimedia extensions and the present media processors. The demand to improve the price-performance ratio for the whole system and to reduce the power consumption makes the media processor evolve into a system processor, which integrates not only the media processor but also the function of a general-purpose microprocessor, various interfaces and DRAMs.

We have developed a parallel image processing RAM (PIP-RAM) which integrates a 16-Mb DRAM and 128 processor elements (PEs) by means of 0. 38-µm CMOS 64-Mb DRAM process technology. It achieves 7. 68-GIPS processing performance and 3. 84-GB/s memory bandwidth with only 1-W power dissipation (@ 30-MHz), and the key to this performance is the DRAM design. This paper presents the key circuit techniques employed in the DRAM design: 1) a paged-segmentation accessing scheme that reduces sense amplifier power dissipation, and 2) a clocked low-voltage-swing differential-charge-transfer scheme that reduces data line power dissipation with the help of a multi-phase synchronization DRAM control scheme. These techniques have general importance for the design of LSIs in which DRAMs and logic are tightly integrated on single chips.

The problem of constructing the proper-path-decomposition of width at most 2 has an application to the efficient graph layout into ladders. In this paper, we give a linear time algorithm which, for a given graph with maximum vertex degree at most 3, determines whether the proper-pathwidth of the graph is at most 2, and if so, constructs a proper-path-decomposition of width at most 2.

We present techniques to implement fair-sharing on both link bandwidth and buffer space in a switch or router. Together they possess the following merits: 1. solving the counter-overflow problem; 2. avoiding the "credit" accumulation issue; 3. integrating bandwidth allocation with buffer management. The simplicity of this method makes it a viable candidate for implementational use on switches and routers.

A two stage Combline Bandpass Filter (C-BPF) of the Vertically Installed Planar (VIP) structure has been investigated, which is essentially composed of a strongly coupled microstrip lines terminated with a planar fin and through-hole combined with the tapping feed approach. The principle and performance of this filter is studied approximately by an equivalent circuit model and also by the normalized 3D-FDTD method more exactly. The time domain iteration in the FDTD analysis is performed in an expanded time dimension resulting in a reduced CPU time. Some of the obtained numerical results are compared well with the measured ones. A modified VIP combline BPF has the advantages of simple structure, easy tuning, low cost, versatile bandwidth control and good skirt characteristics brought about by two attenuation poles.

A traffic engineering method has been developed to meet the requirements for efficient bandwidth dimensioning and for a practical and consolidated network design method. It characterizes the offered-traffic burstiness on a transit link by using time-series measurement of the aggregate traffic. It estimates future traffic characteristics based on the average traffic volume at that time which is easily derived from trend analysis, i. e. , an x% increase in bandwidth each year and gives the required link capacity. Simulation showed that the parameters estimated using this method fit the actual behavior of a network well. This method enables an appropriate bandwidth to be allocated to a transit link without having to estimate the specific traffic characteristics for each connection over the link. Once the burstiness parameter and its trend have been identified based on this method, it is possible to use a simple traffic measurement method to detect changes in network traffic and feed them back to the engineering procedure.

In this paper, a design concept that offers ATM-VP connections with different protection levels is presented. The users have the choice to select the protection level they wish, the network transport service they need, and the worst cell loss they can tolerate at call set up time, and pay accordingly. Besides, an advanced adaptive traffic control scheme that simplifies call and cell processing is also presented. Many important functions such as call admission, VC-bandwidth reservation, cell-level congestion control, etc. are efficiently performed at the boundary of the backbone network. In this way is given a suitable answer to the important question: "How can future telecommunication networks based on ATM provide services with customized availability ?" A platform that outlines the potential interaction between restoration methods and congestion avoidance schemes is also obtained.