This paper presents a power-constrained test scheduling method for multi-clock domain SoCs that consist of cores operating at different clock frequencies during test. In the proposed method, we utilize virtual TAM to solve the frequency gaps between cores and the ATE. Moreover, we present a technique to reduce power consumption of cores during test while the test time of the cores remain the same or increase a little by using virtual TAM. Experimental results show the effectiveness of the proposed method.

This paper studies a method for transforming ordinary cryptographic primitives to new harder primitives. Such a method is expected to lead to general schemes that make present cryptosystems secure against the attack of quantum computers. We propose a general technique to construct a new function from an ordinary primitive function f with a help of another hard function g so that the resulting function is to be new hard primitives. We call this technique a lifting of f by g. We show that the lifted function is harder than original functions under some simple conditions.

This letter deals with multiuser detection under imprecise knowledge of the received signature codes of all active users for multicarrier code division multiple access (MC-CDMA) systems. The weight vector of the modified multiple constrained minimum variance (MMCMV) is found by projecting the multiple constrained minimum variance (MCMV) weight vector onto a vector subspace constructed from the eigenstructure of the correlation matrix. However, MMCMV still cannot handle the large code-mismatch. Shaping the noise subspace with all estimated active spreading codes, we present an effective approach to achieve more robust capabilities than the MMCMV. Computer simulations show the effectiveness of the proposed detector.

Machine learning techniques have long been applied in many fields and have gained a lot of success. The purpose of learning processes is generally to obtain a set of parameters based on a given data set by minimizing a certain objective function which can explain the data set in a maximum likelihood or minimum estimation error sense. However, most of the learned parameters are highly data dependent and rarely reflect the true physical mechanism that is involved in the observation data. In order to obtain the inherent knowledge involved in the observed data, it is necessary to combine physical models with learning process rather than only fitting the observations with a black box model. To reveal underlying properties of human speech production, we proposed a learning process based on a physiological articulatory model and a coarticulation model, where both of the models are derived from human mechanisms. A two-layer learning framework was designed to learn the parameters concerned with physiological level using the physiological articulatory model and the parameters in the motor planning level using the coarticulation model. The learning process was carried out on an articulatory database of human speech production. The learned parameters were evaluated by numerical experiments and listening tests. The phonetic targets obtained in the planning stage provided an evidence for understanding the virtual targets of human speech production. As a result, the model based learning process reveals the inherent mechanism of the human speech via the learned parameters with certain physical meaning.

This paper proposes a very simple method of eliminating the gain and offset errors caused by mismatches of elements, such as capacitors, for a high-speed CMOS pipelined ADC with a 1.5-bit architecture. The gain and offset errors in a bit-block due to capacitor mismatch are analog-to-digital (A-D) converted without correcting errors, but by exchanging capacitors at every clock. The obtained results are digital codes at the output of the ADC, and they contain positive and negative errors in turn. The two consecutive codes are then added in digital form, thus canceling the errors. This results in the two-fold oversampling operation. As the distortion component arises when the input signal frequency increases, a front-end SHA is used to completely eliminate distortion up to the Nyquist frequency. The behavioral simulation of a 14-bit ADC reveals that this CMOS pipelined ADC with a 1.5-bit bit-block architecture, even without a front-end SHA, has more than 70 dB of spurious-free dynamic range (SFDR) for up to an 8 MHz input signal when each of the upper three bit-blocks has gain and offset errors of +0.8% when the clock frequency is 102.4 MHz. Using an SHA in front further improves the SFDR to 95 dB up to the signal frequency bandwidth of 25.6 MHz.

The performance of TCP data transmission deteriorates significantly when a TCP connection traverses a heterogeneous network consisting of wired and wireless links. This is mainly because of packet losses caused by the high bit error rate of wireless links. We proposed receiver-based ACK splitting mechanism in [1]. It is a new mechanism to improve the performance of TCP over wired and wireless heterogeneous networks. Our mechanism employs a receiver-based approach, which does not need modifications to be made to the sender TCP or the base station. It uses the ACK-splitting method for increasing the congestion window size quickly in order to restrain the throughput degradation caused by packet losses due to the high bit error rate of wireless links. In this paper, we develop a mathematical analysis method to derive the throughput of a TCP connection, with/without our mechanism, which traverses wired and wireless heterogeneous networks. By using the analysis results, we evaluate the effectiveness of our mechanism in the network where both of packet losses due to network congestion and those caused by the high bit error rate of wireless links take place. Through An evaluation of the proposed method shows that it can give a good estimation of TCP throughput under the mixture networks of wired/wireless links. We also find that the larger the bandwidth of the wireless link is, the more effective our mechanism becomes, therefore, the mechanism's usability will increase in the future as wireless networks become faster.

The traditional feedback linearization method often requires the full system parameter and state information. In this paper, we consider an asymptotic stabilization problem of a class of feedback linearizable nonlinear systems by using less than the full parameter/state information. First, our approach is to classify system parameters into two categories--'directly used parameters' and 'indirectly used parameters.' Then, a feedback linearizing controller is designed by using only the 'directly used parameters' and the observer is utilized to estimate the transformed states (diffeomorphism) which includes 'indirectly used parameters.' Thus, in our control approach, we use only a partial set of system parameters and partial state information for asymptotic stability. The useful aspects of the proposed scheme are illustrated through an example.

An improved Max-Log-Map (MLM) turbo equalization algorithm called Scaled Max-Log-Map (SMLM) iterative equalization is presented. Simulations show that the scheme can dramatically outperform the MLM besides it is insensitive to SNR mismatch. Unfortunately, its performance is still much worse than that of Log-Map (LM) with exact SNR over high-loss channels. Accordingly, we also propose a new SNR estimation algorithm based on the reliability values of soft output extrinsic information of SMLM decoder. Using the new scheme, we obtain good performance close to that of LM with ideal knowledge of SNR.

We have designed, fabricated and measured a second-order multibit switched-capacitor complex bandpass ΔΣAD modulator to evaluate our new algorithms and architecture. We propose a new structure of a complex bandpass filter in the forward path with I, Q dynamic matching, that is equivalent to the conventional one but can be divided into two separate parts. As a result, the ΔΣ modulator, which employs our proposed complex filter can also be divided into two separate parts, and there are no signal lines crossing between the upper and lower paths formed by complex filters and feedback DACs. Therefore, the layout design of the modulator can be simplified. The two sets of signal paths and circuits in the modulator are changed between I and Q while CLK is changed between high and low by adding multiplexers. Symmetric circuits are used for I and Q paths at a certain period of time, and they are switched by multiplexers to those used for Q and I paths at another period of time. In this manner, the effect of mismatches between I and Q paths is reduced. Two nine-level quantizers and four DACs are used in the modulator for low-power implementations and higher signal-to-noise-and-distortion (SNDR), but the nonlinearities of DACs are not noise-shaped and the SNDR of the ΔΣAD modulator degrades. We have also employed a new complex bandpass data-weighted averaging (DWA) algorithm to suppress nonlinearity effects of multibit DACs in complex form to achieve high accuracy; it can be realized by just adding simple digital circuitry. To evaluate these algorithms and architecture, we have implemented a modulator using 0.18 µm CMOS technology for operation at 2.8 V power supply; it achieves a measured peak SNDR of 64.5 dB at 20 MS/s with a signal bandwidth of 78 kHz while dissipating 28.4 mW and occupying a chip area of 1.82 mm2. These experimental results demonstrate the effectiveness of the above two algorithms, and the algorithms may be extended to other complex bandpass ΔΣAD modulators for application to low-IF receivers in wireless communication systems.

With the rapid development of wireless network technologies, heterogeneous networks with wired and wireless links are becoming common. However, the performance of TCP data transmission deteriorates significantly when a TCP connection traverses such networks, mainly because of packet losses caused by the high bit error rate of wireless links. Many solutions for this problem have been proposed in the past literature. However, most of them have various drawbacks, such as difficulties in their deployment by the wireless access network provider and end users, violation of TCP's end-to-end principle by splitting the TCP connection, or inapplicability to IP-level encrypted traffic because the base station needs to access the TCP header. In this paper, we propose a new mechanism without such drawbacks to improve the performance of TCP over wired and wireless heterogeneous networks. Our mechanism employs a receiver-based approach, which does not need modifications to be made to the sender TCP or the base station. It uses the ACK-splitting method for increasing the congestion window size quickly in order to restrain the throughput degradation caused by packet losses due to the high bit error rate of wireless links. We evaluate the performance of our mechanism and show that our mechanism can increase throughput by up to 94% in a UMTS network. The simulation results also show that our mechanism does not significantly deteriorate even when the receiver cannot perfectly distinguish whether packet losses are due to network congestion or bit errors on the wireless links.

High power consumption and slow access of enlarged and multiported register files make it difficult to design high performance superscalar processors. The clustered architecture, where the conventional monolithic register file is partitioned into several smaller register files, is expect to overcome the register file issues. In the clustered architecture, the more a monolithic register file is partitioned, the lower power and faster access register files can be realized. However, the partitioning causes losses of IPC (instructions per clock cycle) due to communication among register files. Therefore, degree of partitioning has a strong impact on the trade-off between power consumption and performance. In addition, the organization of partitioned register files also affects the trade-off. In this paper, we attempt to investigate appropriate degrees of partitioning and organizations of partitioned register files in a clustered architecture to assess the trade-off. From the results of execute-driven simulation, we find that the organization of register files and the degree of partitioning have a strong impact on the IPC, and the configuration with non-consistent register files can make use of the partitioned resources more effectively. From the results of register file access time and energy modeling, we find that the configurations with the highly partitioned non-consistent register file organization can receive benefit of the partitioning in terms of operating frequency and access energy of register files. Further, we examine relationship between IPS (instructions per second) and the product of IPC and operating frequency of register files. The results suggest that highly partitioned non-consistent configurations tends to gain more advantage in performance and power.

Network emulation system constructs a virtual network environment which has the characteristics of controllable and repeatable network conditions. This makes it possible to predict the correctness and performance of proposed new technology before deploying to Internet. In this paper we present a methodology for evaluating the correctness and performance of applications based on the PARNEM, a parallel discrete event network emulator. PARNEM employs a BSP based real-time event scheduling engine, provides flexible interactive mechanism and facilitates legacy network models reuse. PARNEM allows detailed and accurate study of application behavior. Comprehensive case studies covering bottleneck bandwidth measurement and distributed cooperative web caching system demonstrate that network emulation technology opens a wide range of new opportunities for examining the behavior of applications.

Since the control input of a feedback linearizable system depends on the diffeomorphism, the transient behavior of the controlled system is different. In this paper, we propose a switching rule for selecting a diffeomorphism so that the transient behavior is improved and the switched system is stable. Specifically, we show the sufficient condition for the exponential stability and the exponential upper bound of the trajectory of the switched system.

A multiple-places reservation discipline is studied in a discrete-time priority queueing system. We obtain the joint distribution of system state, from which the delays of high and low priority packets are derived. Comparison is made with the cases of FIFO, single-place reservation discipline and HOL priority.

A novel approach of robust adaptive beamforming (RABF) is presented in this paper, aiming at robustness against both finite-sample effects and steering vector mismatches. It belongs to the class of diagonal loading approaches with the loading level determined based on worst-case performance optimization. The proposed approach, however, is distinguished by two points. (1) It takes finite-sample effects into account and applies worst-case performance optimization to not only the constraints, but also the objective of the constrained quadratic equation, for which it is referred to as joint worst-case RABF (JW-RABF). (2) It suggests a simple closed-form solution to the optimal loading after some approximations, revealing how different factors affect the loading. Compared with many existing methods in this field, the proposed one achieves better robustness in the case of small sample data size as well as steering vector mismatches. Moreover, it is less computationally demanding for presenting a simple closed-form solution to the optimal loading. Numerical examples confirm the effectiveness of the proposed approach.

It is known that any chordal graph can be uniquely decomposed into simplicial components. Based on this fact, it is shown that for a given chordal graph, its automorphism group can be computed in O((c!n)O(1)) time, where c denotes the maximum size of simplicial components and n denotes the number of nodes. It is also shown that isomorphism of those chordal graphs can be decided within the same time bound. From the viewpoint of polynomial-time computability, our result strictly strengthens the previous ones respecting the clique number.

This letter proposes a compensation method that can alleviate the problem of I/Q mismatch generated in the direct-conversion receiver of OFDM systems. In the proposed method, the amount of I/Q mismatch is estimated using null-carriers in transmitted signals, and it is subtracted from received symbols to suppress I/Q mismatch effects. Simulations show experiments that the proposed method can effectively eliminate the I/Q mismatch effects.

The boundary of a distributed denial of service (DDoS) attack, one of the most threatening attacks in a wired network, now extends to wireless mobile networks, following the appearance of a DDoS attack tool targeted at mobile phones. However, the existing defense mechanisms against such attacks in a wired network are not effective in a wireless mobile network, because of differences in their characteristics such as the mobile possibility of attack agents. In this paper, we propose a proactive defense mechanism against IP spoofing traffic for mobile networks. IP spoofing is one of the features of a DDoS attack against which it is most difficult to defend. Among the various mobile networks, we focus on the Network Mobility standard that is being established by the NEMO Working Group in the IETF. Our defense consists of following five processes: speedy detection, filtering of attack packets, identification of attack agents, isolation of attack agents, and notification to neighboring routers. We simulated and analyzed the effects on normal traffic of moving attack agents, and the results of applying our defense to a mobile network. Our simulation results show that our mechanism provides a robust defense.

The RC mismatch among S/H stages for time-interleaved ADCs causes a phase error and a gain error and the phase error is dominant. The paper points out that clock skew and the phase error caused by the RC mismatch have similar effects on the sampling error and then can be compensated with the clock skew compensation. Simulation results agree well with the theoretical analysis. With the phase error compensation of RC mismatch, the SNDR in 14b ADC can be improved by more than 15 dB in the case that the bandwidth of S/H circuits is 3 times the sampling frequency. This paper also proposes a method of clock skew and RC mismatch compensation in time-interleaved sample-and-hold (S/H) circuits by sampling clock phase adjusting.

We propose an optimal algorithm for the real-time scheduling of parallel tasks on multiprocessors, where the tasks have the properties of flexible preemption, linear speedup, bounded parallelism, and arbitrary deadline. The proposed algorithm is optimal in the sense that it always finds out a feasible schedule if one exists. Furthermore, the algorithm delivers the best schedule consuming the fewest processors among feasible schedules. In this letter, we prove the optimality of the proposed algorithm. Also, we show that the time complexity of the algorithm is O(M2N2) in the worst case, where M and N are the number of tasks and the number of processors, respectively.