A multicast error control protocol proposed by Metzner is generalized and the performance of the proposed protocol on random error channels (binary symmetric channels) is analyzed. The proposed protocol adopts an encoding procedure based on a product code structure, whith enables each destined user terminal to decode the received frames with the Reddy-Robinson algorithm. As a result, the performance degradation due to the re-broadcasting of the replicas of the previously transmitted frames can be circumvented. The numerical results for the analysis and the simulation indicate that the proposed protocol yields higher throughput and less degradation of throughput with an increase of the number of destined terminals.

Separability is a valuable property of nonlinear mappings. By exploiting this property, computational complexity of many numerical algorithms can be substantially reduced. In this letter, a new algorithm is presented that detects the separability of nonlinear mappings using the concept of "computational graph". A hybrid algorithm using both the top-down search and the bottom-up search is proposed. It is shown that this hybrid algorithm is advantageous in detecting the separability of nonlinear simultaneous functions.

For the connection request procedure in mobile communication systems, a previous study had shown that the 3-channel systems provide the haighest maximum of stable per channel throughput. In this paper, we propose and study a new algorithm, called the Parallel Collision Resolution Algorithm, which can be implemented in a Q-channel connection request environment, where Q3. For the implementation, the channels are arranged in R groups, where R is a positive integer. The collision resolution scheme distributes the collided messages over all the groups so that throughput and delay measures can be improved. At any point in time, there can be a maximum of R collision resolution schemes operational irrespective of the channel or the group number over which collisions occurred. The performance measures are estimated by computer simulation. Under the new algorithm, almost the same level of the perchannel stable throughput measure of a 3-channel network can be achieved in networks for which Q3. This feature allows freedom to the network designer to employ a higher number of connection request channels without forfeiting high channel utilization rates. When Q is an integral multiple of 3, the maximum stable per channel throughput level achieved can be the same as that achieved by the 3 channel system, if the grouping of channels is such that each group consists of 3 channels. When Q is not an integral multiple of 3, the intuitive strategy of organizing the channels in such a way that Q/3 groups consist of 3 channels each and one group consists of (Q mod 3) channels, may result in much degraded performance. It is found that, if the channels are so organised that no group is composed of (Q mod 3) channels, the performance levels can be substantially enhanced. Also, under the new algorithm, the delay measure is significantly improved, particularly in schemes like the mobile satellite systems with high propagation delays. We conclude that the new scheme presents a promising collision resolution methodology for connection request procedures.

The design of N-dimensional (N-D) FIR filters requires in general an enormous computational effort. One of the most successful methods for design and implementation is the McClellan transformation. In this paper a numerically simple technique for determining the coefficients of the transformation is suggested. This appears to be the simplest available method for the design of N-D hyperspherically symmetric FIR filters with excellent symmetry.

A non-blocking optomechanical matrix switch has been developed that is assembled using cassettes as units. Switching can be accomplished between two ferrule-terminated-fiber groups by automatic disconnection and reconnection. The fabricated 100100, 3.1-mm-ferrule-pitch, 710W490D500H (mm) switch exhibits a mean insertion loss of 0.78dB in the 1.31-µm wavelength.

This letter describes an MOS operational transconductance amplifier and an MOS four-quadrant analog multiplier using the quadritail cell, which provides an output current proportional to the square of a differential input voltage. As a result, a linear transconductance amplifier and a quarter-squarer multiplier can be obtained in theoretical circuit analysis.

A model for time spread-pulse position modulation (TS-PPM)/code division multiple access (CDMA) systems is presented. A TS signal is produced by a TS-filter, whose characteristic is a pseudonoise sequence in frequency domain. The error probability performance is analyzed and compared with those of on-off keying (OOK) and binary phase shift keying (BPSK). It is shown that at the same transmission speed TS-PPM is superior to TS-OOK and TS-BPSK due to the dramatic decrease of multiple access interference. The throughput of the network is analyzed, and its relation to the length of pseudonoise sequence and the packet length is also discussed.

To improve the stability and the power supply rejection ratio (PSRR) of the voltage limiter circuit used in high-density DRAM's we present a voltage limiter circuit with pole-zero compensation. Analytical expressions that describe the stability of the circuit are provided for comprehensive consideration of circuit design. Voltage limiters with pole-zero compensation are shown to have excellent performance with respect to the stability, PSRR, and circuit area occupation. The parasitic resistances in internal voltage supply lines, signal transmission lines, and transistors are important parameters determining the stability of pole-zero compensation. Evaluation of a 16-Mbit test device revealed internal voltage fluctuations of 6% during operation of a chip-internal circuit, a phase margin of 53, and a PSRR of 30 dB.

This paper proposes a new fault tolerant intercommunication scheme for real-time operations and three new interconnection networks to construct a fault tolerant multi-processor system for pipeline processings. The proposed intercommunication scheme using bank memory switching technique has an advantage to make a fault tolerant pipeline system so that it can detect any failure caused in a processing element of the system. In addition, it can overcome conventional problems caused in interconnection circuits to flow data with one way direction such as a pipeline processing.

This paper presents a new type of zero-voltage-switched (ZVS) push-pull dc-dc converter with two synchronous rectifiers in the secondary circuit. ZVS is realized using the magnetizing current of the transformer as a constant current source during the commutation. The output voltage is controlled by PWM with a constant switching frequency. The circuit operation is described using equivalent circuits. The steady-state and dynamic characteristics are analyzed and confirmed experimentally.

There have been few studies on formal approaches to the specification and realization of asynchronous sequential circuits. For synchronous sequential circuits, an algebraic method is proposed as one of such approaches, but it cannot be applied to asynchronous ones directly. This paper describes an algebraic method of specifying the abstract behavior of asynchronous sequential circuits. We select an daisy chain arbiter as an example of them. In the arbiter, state transitions are caused by input changes, and all the modules do not always make state transitions simultaneously. These are main obstacles to specify it in the same way as sychronous sequential circuits. In order to remove them, we modify the meaning of input in specifications and introduce pseudo state transitions so that we can regard all the modules as if they make state transitions simultaneously. This method can be applied to most of the other asynchronous sequential circuits.

The characteristics of voltage-resonant dc-dc converters have already been analyzed and described. However, in the conventional analysis, the inductance of the reactor is assumed to be infinity and the loss resistance of the power circuit is not taken into account. Also, in some cases, the averaging method is applied to analyze the resonant dc-dc converters as well as the pwm dc-dc converters. Consequently, the results from conventional analysis are not entirely in agreement with the experimental ones. This paper presents a general design-oriented analysis of the buck-boost type voltage-resonant dc-dc converter in the continuous and discontinuous modes of the reactor current. In this analysis, the loss resistance in each part of the power circuit, the inductance of the reactor, the effective value (not mean value) of the power loss, and the energy-balance among the input, output and internal-loss powers are taken into account. As a result, the behavior and characteristics of the buck-boost type voltage-resonant dc-dc converter are fully explained. It is also revealed that there is a useful mode in the discontinuous reactor current region, in which the output voltage can be regulated sufficiently for the load change from no load to full load and for the relatively large change of the input voltage, and then the change in the switching frequency can be kept relatively small.

A new circuit and a transformer structure is described for a high-input-voltage converter operating at a high switching frequency. The two-MOSFET forward converter is suitable for a high-input-voltage converter. To increase the switching frequency, the reset period of the transformer core flux must be reduced. There are a few methods for decreasing the reset period. Increasing the transformer flyback voltage and reducing its stray capacitance are effective in decreasing the reset period without increasing power loss. A new two-MOSFET forward converter is proposed which uset the increased flyback voltage and a transformer structure to reduce the stray capacitance. The new converter using this transformer provides the basis for a 48-V, 100-W output, 270-V input converter operating at 200kHz with high efficiency (above 95%).

This paper describes a new soft-error-immune SICOS upward transistor memory cell suitable for ultra-high-speed bipolar RAMs. A cell size of 180 µm2, significantly smaller than the 500 µm2 in the conventional upward transistor cell, is achieved by marging an upward transistor and a Shottky barrier diode. A new very thin polysilicon resistor and 0.5-µm U-groove isolated SICOS technology are used to furher reduce cell size. The memory cell is about 105 times as immune to soft errors as downward transistor cells. A simulation shows that a 256-Kbit RAM with a write cycle time below 3 ns can be made using this memory cell.

This article discusses a synthesis procedure of a discrete-time asynchronous neural network whose information is a limit cycle. The synthesis procedure uses a novel connection matrix and can be reduced into a linear epuation. If all elements of desired limit cycles are independent at each transition step, the equation can be solved and all desired limit cycles can be stored. In some experiments, our procedure exhibits much better storing performance than previous ones.

This paper relates to a novel algorithm for fast estimation of the coefficients of the adaptive FIR filter. The novel algorithm is derived from a first order IIR filter experssion clarifying the estimation process of the NLMS (normalized least mean square) algorithm. The expression shows that the estimation process is equivalent to a procedure extracting the cross-correlation coefficient between the input and the output of an unknown system to be estimated. The interpretation allows to move a subtraction of the echo replica beyond the IIR filter, and the movement gives a construction with the IIR filter coefficient of unity which forms the arithmetic mean. The construction in comparison with the conventional NLMS algorithm, improves the covergence rate extreamly. Moreover, when we use the construction with a simple technique which limits the term of calculating the correlation coefficient in the beginning of a convergence process, the convergence delay becomes negligible. This is a very desirable performance for acoustic echo canceller. In this paper, double-talk and echo path fluctuation are also studied as the first stage for application to acoustic echo canceller. The two subjects can be resolved by introducing two switches and delays into the evaluation process of the correlation coefficient.

In developing the SXO operating system for the SURE SYSTEM 2000 continuous operation system, we aimed to create an unprecedentedly high software and hardware fault tolerance. We devised a fault tolerant architecture and various methodologies to ensure fault tolerance. We implemented these techniques systematically throughout operating system development. In the design stage, we developed a design methodology called the recovery process chart to verify that recovery mechanisms were complete. In the manufacturing stage, we applied the concept of critical routes to recovery and other processes essential to high dependability. We also developed a method of finding critical routes in a recovery process chart. In the test stage, we added an artificial software fault injection mechanism to the operating system. It generates various reproducible errors at appropriate times and reduces the number of personnel needed for test, making system reliability evaluation easy.

This paper presents a new architecture of a copy network which employs the principle of recursive generation of copy cells. The proposed architecture achieves high utilization of the links and buffers of the copy network, and preserves the cell sequence. The architecture lends itself modularity so that large multicast ATM switches can be fabricated by employing the proposed copy network. Two different modular structures - one for reduced latency of the unicast cell and the master cell from which copies are made, and the other for reduced hardware overhead - for realizing large multicast ATM switches are configured. The hardware of functional elements of the copy network are the same as those of the functional elements of a modular point-to-point switch proposed earlier, thereby resulting in the modularity of functional elements as well. Simulation studies show that the proposed copy network achieves high throughput and low cell loss probability, and the required buffer sizes are small. The delay of cells is found to be very small for traffic loads up to 90%.

Actual debugging actions during the testing phase in the software development and the operation phase are not always performed perfectly. In other words, all detected software faults are not corrected and removed certainly. Generally, this is called imperfect debugging. In this paper, we discuss a software reliability growth model considering imperfect debugging that faults are not always corrected/removed when they are detected. Defining a random variable representing the cumulative number of faults corrected up to a specified testing time, this model is described by a semi-Markov process. We derive various quantitative measures for software reliability assessment and show their numercal examples.

This paper proposes a new adaptive algorithm for acoustic echo cancellers with four times the convergence speed for a speech input, at almost the same computational load, of the normalized LMS (NLMS). This algorithm reflects both the statistics of the variation of a room impulse response and the whitening of the received input signal. This algorithm, called the ESP (exponentially weighted step-size projection) algorithm, uses a different step size for each coefficient of an adaptive transversal filter. These step sizes are time-invariant and weighted proportional to the expected variation of a room impulse response. As a result, the algorithm adjusts coefficients with large errors in large steps, and coefficients with small errors in small steps. The algorithm is based on the fact that the expected variation of a room impulse response becomes progressively smaller along the series by the same exponential ratio as the impulse response energy decay. This algorithm also reflects the whitening of the received input signal, i.e., it removes the correlation between consecutive received input vectors. This process is effective for speech, which has a highly non-white spectrum. A geometric interpretation of the proposed algorithm is derived and the convergence condition is proved. A fast profection algorithm is introduced to reduce the computational complexity and modified for a practical multiple DSP structure so that it requires almost the same computational load, 2L multiply-add operations, as the conventional NLMS. The algorithm is implemented in an acoustic echo canceller constructed with multiple DSP chips, and its fast convergence is demonstrated.