A new transfer mode and a switching architecture which can support loss free and no delay jitter service class with shorter switching delay compared with "stop and go queueing scheme" is proposed. This scheme combines ATM scheme with hierarchical STM framing concept.

To improve measurement accuracy and speed, a switched-capacitor capacitance measurement circuit with the vernier scale is developed. Its process consists of a coarse measurement by charge-balancing A-D conversion and a fine measurement by single-slope A-D conversion. a prototype using discrete components confirms the principles of operation.

Switched-current (SI) is a current-mode analog sampled-data signal processing technique realizable in standard digital CMOS technologies. In this paper, new switched-current (SI) mirrors using OTAs (operational transconductance amplifiers) are proposed. These circuits are less sensitive to clock-feedthrough noise than conventional SI mirrors by virtue of linear I-V/V-I transformations. In addition, the current gain of the proposed mirror is electronically tunable. Not only inverting mirrors but also noninverting mirrors can be realized by this method.

The performance of analog circuits is strongly influenced by their layout. Performance specifications are usually translated into physical constraints such as symmetry, common orientation, and distance constraints among certain components. Automatic digital layout tools can be adopted and modified to deal with the imposed performance constraints on the analog layout. The selection and modifications of algorithms to handle the analog constraints became the area of research in analog layout systems. The existing systems are characterized by the use of stochastic optimization techniques based placement, grid based or channel routers, and lack of compaction. In this paper, algorithms for analog circuit placement, routing, and compaction are presented. The proposed algorithms consider the analog oriented constraints, which are important from an analog layout point of view, and reduce the computation cost. The placement algorithm is based on a force directed method and consists of two main phases, each of which includes a tuning procedure. In the first phase, we solve a set of simultaneous linear equations, based upon the attractive forces. These attractive forces represent the interconnection topology of given blocks and some specified constraints. Symmetry constraint is considered throughout the tuning procedure. In the second phase, block overlap resulting from the first phase is resolved iteratively, where each iteration is followed by the symmetry tuning procedure. Routing is performed using a line expansion based gridless router. Routing constraints are taken into account and several routing priorities are imposed on the nets. The compactor part employs a constraint graph based algorithm while considering the analog symmetry constraints. The algorithms are implemented and integrated within an analog layout design system. An experimental result for an OP AMP provided by MCNC benchmark is shown to demonstrate the performance of the algorithms.

This paper deals with the uniqueness of a solution of the basic equation obtained from the analysis of resistive circuits including ideal diodes. The equation in consideration is of the type of (A-)X=b, where A is a constant matrix, b a constant vector, X an unknown vector satisfying X 0, and a diagonal matrix whose diagonal elements take the value 0 or 1 arbitrarily. The necessary and sufficient conditions for the equation to have a unique solution X 0 for an arbitrary vector b are shown. Some numerical examples are given for the illustration of the result.

Oversampled analog-to-digital (A/D) converters based on sigma-delta (ΣΔ) modulation are attractive for VLSI implementation because they are especially tolertant of circuit nonidealities and component mismatch. Oversampled ΣΔ modulator has some points which must be improved. Some of these problems are based on the small input signal and the integrator leak. In this paper,ΣΔ A/D converter having a dither circuit to improve the linearity and the compensation technique of the integer leak are presented. By the simulation, the most suitable dither to improve the linearity of the modulator is obtained as follows: the amplitude is 1/150 of input signal maximum amplitude, the frequency is 4-times of the signal-band. Using the compensation circuit of the integrator leak, 72 dB of dynamic range is obtained when op-amp gain is 30 dB.

By a measure we mean a function µ from {0, 1}* (the set of all binary sequences) to real numbers such that µ(x)0 and µ({0, 1}*). A malign measure is a measure such that if an input x in {0, 1}n (the set of all binary sequences of length n) is selected with the probability µ(x)/µ ({0, 1}n) then the worst-case computation time tWOA (n) and the average-case computation time tav,µA(n) of an algorithm A for inputs of length n are functions of n of the same order for any algorithm A. Li and Vitányi found that measures that are known as a priori measures are malign. We prove that a priori" -ness and malignness are different in one strong sense.

This paper presents efficient algorithms for finding the largest tree S such that there are vertex disjoint subtrees S1, , S (k1) of T each of which is isomorphic to S and every leaf of T is a leaf of some Si. The algorithms are useful for learning a macro table.

The most commonly used activation function in Backpropagation learning is sigmoidal while linear function is also sometimes used at the output layer with the view that choice between these activation functions does not make considerable differences in network's performance. In this letter, we show distinct performance between a network with linear output units and a similar network with sigmoid output units in terms of convergence behavior and generalization ability. We experimented with two types of cost functions, namely, sum-squared error used in standard Backpropagation and log-likelihood recently reported. We find that, with sum-squared error cost function and hidden units with nonsteep sigmoid function, use of linear units at the output layer instead of sigmoidal ones accelerates the convergence speed considerably while generalization ability is slightly degraded. Network with sigmoid output units trained by log-likelihood cost function yields even faster convergence and better generalization but does not converge at all with linear output units. It is also shown that a network with linear output units needs more hidden units for convergence.

The hierarchies of multihead finite automata over a one-letter alphabet are investigated. Let SeH(k) [NSeH(k) ] denote the class of languages over a one-letter alphabet accepted by deterministic [nondeterministic] sensing two-way k-head finite automata. Let H (k)s[NH(k)s] denote the class of sets of square tapes over a one-letter alphabet accepted by two-dimensional four-way deterministic [nondeterministic] k-head finite automata. Let SeH(k)s[NSeH(k)s] denote the class of sets of square tapes over a one-letter alphabet accepted by two-dimensional four-way sensing deterministic [nondeterministic] k-head finite automata. This paper shows that SeH(k) SeH(k1) and NSeH(k) NSeH(k1) hold for all k3. It is also shown that H(k)s[NH(k)s] H(k1)s[NH (k1)s] and SeH (k)s[NSeH(k)s] SeH(k1)s[NSeH(k1)s] hold for all k1.

This letter presents a technique to cancel the parasitic effects of operational amplifier (op amp) in active filter design. To minimize the effects, an op amp model considering the parasitics (i.e. both parasitic poles and zeros) is utilized. It is shown that undesirable factors in the transfer function due to the parasitics can be canceled well by predistorting the passive element values of the circuit. As an example, an active-R highpass filter is evaluated both theoretically and numerically. In this way, the proposed technique can be effectively incorporated into the design of active filters.

Behavior modeling of objects is critical in object-oriented design. In particular, it is essential to preserve integrity constraints on object behavior in application environments where objects of various classes dynamically interact with each other. In order to provide a stable design technique, a behavior model using the notion of the life cycle schema of a class is proposed. To model the aspect of behavioral abstraction of objects, the notion of schema refinement together with a diagrammatic representation technique is also defined. In this framework, a formalization of behavior constraints on objects which interact with each other is proposed together with its graphical representation. Verification rules of consistency of behavior constraints are also discussed. In order to perform certain functions, several partner objects of the same or different classes should collaborate establishing client-server relationships. The contract of a class is defined as a collection of responsibilities of a server class to a client class where each responsibility is specified in the form of the script. To achieve a high degree of systems integrity, a procedure to derive scripts from behavior constraints on collaborating partners is developed. It is also critical to evenly distribute responsibilities to partner objects. A delegation is placing a whole or a part of responsibilities of an object in charge of other objects. Based on the design principle delegation along the aggregation hierarchy,' a unified design approach to delegation that enables to reorganize scripts in constraints preserving way is proposed.

The main result of this paper is an almost-everywhere hierarchy theorem for nondeterministic space that is as tight as the well-known infinitely-often hierarchy theorems for deterministic and nondeterministic space. In addition, we show that the complexity-theoretic notion of almost-everywhere complex functions is identical to the recursion-theoretic notion of bi-immune sets in the nondeterministic space domain. Finally, we investigate bi-immunity in nondeterministic and alternating time complexity classes and derive a similar hierarchy result for alternating time.

As is well known, Linard's equation +µf (χ)+g(χ)=0 represents a wide class of oscillatory circuits as an extension of van der Pol's equation, and Linard's theorem guarantees the existence of a unique periodic solution which is orbitally stable. However, we sometimes meet such cases in engineering applications that the symmetry of the equation is violated, for instance, by a constant bias force. While, it has been known that asymmetric Linard's equation can have more than one periodic solution. The problem of finding the maximum number of such solutions, known as a special case of Hilbert's sixteenth problem, has recently been solved by T. Koga, one of the present authors. This paper first describes fundamental theorems due to T. Koga, and presents a solution to the synthesis problem of asymmetric Linard's systems, which generates an arbitrarily prescribed number of limit cycles, and which is considered to be important in relation to the stability of Linard's systems. Then, as application of this result, we give a method of determining parameters included in Linard's systems which may produce two limit cycles depending on the parameters. We also give a Linard's system which have three limit cycles. In addition, a new result on the parameter dependency of the number of limit cycles is presented.

This paper presents a general form and a set of basic gates to implement (K+1)-valued PLA structure logic circuits. A complete fault analysis on the proposed circuit has been done and it is shown that all fanout stem faults can be collapsed to branch faults. A procedure for fault collapsing is derived. For any function implemented in the (K+1)-valued circuit, the number of remaining faults is smaller than that of the 2-valued circuit after the collapsing, where the value of K is dependent on the number of outputs and the assignment of the OR plane of the 2-valued logic circuit.

A superresolution technique is considered for use in antenna gain measurements. A modification of the MUSIC algorithm is employed to resolve incident signals separately in the time domain. The modification involves preprocessing the received data using a spatial scheme prior to applying the MUSIC algorithm. Interference rejection in the antenna measurements using the fast Fourier transform (FFT) based techniques have been realized by a recently developed vector network analyzer, and its availability has been reported in the literature. However, response resolution in the time domain of these conventional techniques is limited by the antenna bandwidth. The MUSIC algorithm has the advantage of being able to eliminate unwanted responses when performing antenna measurements in situations where the antenna band-width is too narrow to support FFT based techniques. In this paper, experimental results of antenna gain measurements in a multipath environment show the accuracy and resolving power of this technique.

This paper briefly considers future broadcasting technologies, including digital television as a system for the near future and three-dimensional television as a part of a system to be developed rather later. However, due to limitations of space, this paper discusses only video technologies in detail. First, the status of bit reduction technologies for digital television is described and then satellite digital broadcasting and terrestrial digital broadcasting are also discussed. The authors stress the necessity of the further development of digital video compression technologies. Later, we discuss three-dimensional television, we describe requirements for the service and the present status of the technologies. And last, the paper considers the future prospects for a three-dimensional television service.

Recently, studies aiming at the next generation of visual communication services which support better human communication have been carried out intensively in Japan. The principal motive of these studies is to develop new services which are not restricted to a conventional communication framework based on the transmission of waveform signals. This paper focuses on three important key words in these studies; "intelligent," "real," and "distributed and collaborative," and describes recent research activities. The first key word "intelligent" relates to intelligent image coding. As a particular example, model-based coding of moving facial images is discussed in detail. In this method, shape change and motion of the human face is described by a small number of parameters. This feature leads to the development of new applications such as very low bit-rate transmission of moving facial images, analysis and synthesis of facial expression, human interfaces, and so on. The second key word "real" relates to communication with realistic sensations and virtual space teleconferencing. Among various component technologies, real-time reproduction of 3-D human images and a cooperative work environment with virtual space are discussed in detail. The last key word "distributed and collaborative" relates to collaborative work in a distributed work environment. The importance of visual media in collaborative work, a concept of CSCW, and requirements for realizing a distributed collaborative environment are discussed. Then, four examples of CSCW systems are briefly outlined.

In this paper, the characteristics of microstrip lines near the edge of dielectric substrate are analyzed by improving the rectangular boundary division method. The numerical results indicate the changes of the characteristics of a microstrip line when the strip conductor is closely located to the edge. When the distance the dielectric substrate edge to the strip conductor is less than the thickness of dielectric substrate, the effects of the edge on the line characteristics are no longer negligible. The numerical results in this paper show high computation accuracy without increasing computation time. Our improvement is effective for the analysis of the microstrip lines both for the narrow strip conductor and the strip conductor close to the edge. The relative errors between the numerical results and the measured values are less than 1.2%.

The Viterbi algorithm is a well-established technique for channel and source decoding in high performance digital communication systems. However, excessive time consumption makes it difficult to design an efficient high-speed decoder for practical application. This paper describes the implementation of parallel Viterbi algorithm by multi-microprocessors. Internal computations are performed in a parallel fashion. The use of microprocessors allows low-cost implementation with moderate complexity. The software and hardware implementations of the Viterbi algorithm on parallel multi-microprocessors for real-time decoding are presented. The implemented method is based on a combination of forming a set of tables and calculations. For efficient operation under fully parallel Viterbi decoding by microprocessors, we considered: (1) branch metrics processing, path metrics updating, path memory updating and decoding output for microprocessor, (2) efficient decomposition of the sequential Viterbi algorithm into parallel algorithms, (3) minimization of the communication among the microprocessors. The practical solutions for the problems of synchronization among the miroprocessors, interconnection network for communication among the microprocessors and memory management are discussed. Furthermore the performance and the speed of the parallel Viterbi decoding are given. For a fixed processing speed of given hardwares, parallel Viterbi decoding allows a linear speed up in the throughput rate with a linear increase in hardware complexity.