Existing algorithmic debugging methods which can locate faults under the guidance of a system have a number of shortcomings. For example, some cannot be applied to imperative languages with side effects; some can locate a faulty function but cannot locate a faulty statement; and some cannot detect faults related to missing statements. This paper presents an algorithmic critical slice-based fault-locating method for imperative languages. Program faults are first classified into two categories: wrong-value faults and missing-assignment faults. The critical slice with respect to a variable-value error is a set of statements such that (1) a wrong-value fault contained in any instruction in the critical slice may have caused that variable-value error, and (2) a wrong-value fault contained in any instruction outside the critical slice could never have caused that variable-value error. The paper also classifies errors found during program testing into three categories: wrong-output errors, missing-output errors, and infinite-loop errors with no output. It finally shows that it is possible to algorithmically locate any fault, including missing statements, for each type of error.

A cyclic analog-to-digital (A/D) converter is developed which accomplishes an n-b conversion in n/2 clock cycles. The architecture consists of two 1-b quantizers connected in a loop. A CMOS design of the 1-b quantizer is given to evaluate the performance of the A/D converter when implemented using presently available process. Spice simulations and error analyses show that a resolution higher than 10-b and a sampling rate up to 1.4 Msps are attainable with a 3-µm CMOS process. A prototype converter breadboarded using discrete components has confirmed the principles of operation and error analyses. The device count and the power consumption are small compared to those of a successive-approximation A/D converter. A chip area required for the CMOS implementation is also small because only four unit capacitors are involved. Therefore, the architecture proposed herein is most suited for high accuracy, medium speed A/D conversion.

A new computer architecture using multiwavelength optoelectronic integrated circuits (OEICs) is proposed to attack the problems caused by interconnection complexity. Multiwavelength-OEIC architecures, where various wavelengths are employed as information carriers, provide the wavelength as an extra dimension of freedom for parallel processing, so that we can perform several independent computations in parallel in a single optical module using the wavelength space. This multiplex computing" enables us to reduce the wiring area required by a network and improve their complexity. In this paper, we discuss the efficient multiplexing of Batcher's bitonic sorting networks, highly parallel computing architectures that require global interconnections inherently. A systematic multiplexing of interconnection topology is presented using a binary representation of the connectivities of interconnection paths. It is shown that the wiring area can be reduced by a factor of 1/r2 using r kinds of wavelength components.

By adding a linear resistor in series with the inductor in Chua's circuit, we obtain a circuit whose state equation is topologically conjugate (i.e., equivalent) to a 21-parameter family C of continuous odd-symmetric piecewise-linear equations in R3. In particular, except for a subset of measure zero, every system or vector field belonging to the family C, can be mapped via an explicit non-singular linear transformation into this circuit, which is uniquely determined by 7 parameters. Since no circuit with less than 7 parameters has this property, this augmented circuit is called an unfolding of Chua's circuit--it is analogous to that of "unfolding a vector field" in a small neighborhood of a singular point. Our unfolding, however, is global since it applies to the entire state space R3. The significance of the unfolded Chua's Circuit is that the qualitative dynamics of every autonomous 3rd-order chaotic circuit, system, and differential equation, containing one odd-symmetric 3-segment piecewise-linear function can be mapped into this circuit, thereby making their separate analysis unnecessary. This immense power of unification reduces the investigation of the many heretofore unrelated publications on chaotic circuits and systems to the analysis of only one canonical circuit. This unified approach is illustrated by many examples selected from a zoo of more than 30 strange attractors extracted from the literature. In addition, a gallery of 18 strange attractors in full color is included to demonstrate the immensely rich and complex dynamics of this simplest among all chaotic circuits.

The self-organization rule of planar neural networks has been proposed for learning of 2D distributions. However, it cannot be applied to 3D objects. In this paper, we propose a new model for global representation of the 3D objects. Based on this model, global topology reserving self-organization is achieved using parallel local competitive learning rule such as Kohonen's maps. The proposed model is able to represent the objects distributively and easily accommodate local features.

A low-voltage, high-speed 4-bit CMOS single chip microprocessor, with instruction execution time of 1.0µs at a power supply voltage of 1.8V, has been developed. A single chip processor generally includes crystal oscillation circuits to generate a system clock or a time-base clock. But when the operating voltage is lowered, it becomes difficult to get oscillations to start reliably and to continue stably. This paper describes a low voltage circuit design method for built-in crystal oscillators. Simple design equations for oscillation starting voltage and oscillation starting time are introduced. Then effects of the circuit device parameters, such as power supply voltage, loop gain values, and subthreshold swing S, on the low voltage performance of the crystal oscillators are considered. It is shown that the crystal oscillators operate in a tailing (subthreshold) region at voltages lower than about 1.8 V. Subthreshold swing, threshold voltage, and open loop gain have a significant influence on low voltage oscillation capability. This design method can be applied to crystal oscillators for a wide range of operating voltages.

A new optimal nonlinear regulator design method is developed by applying a multi-layered neural network and a fixed point theorem for a nonlinear controlled system. Based on the calculus of variations and the fixed point theorem, an optimal control law containing a nonlinear mapping of the state can be derived. Because the neural network has not only a good learning ability but also an excellent nonlinear mapping ability, the neural network is used to represent the state nonlinear mapping after some learning operations and an optimal nonlinear regulator may be formed. Simulation demonstrates that the new nonlinear regulator is quite efficient and has a good robust performance as well.

In this paper, a synthesizing method is proposed for the design of discrete-time cellular neural networks for binary image processing. Based on the theory of digital-logical design paradigm of threshold logic, the template parameters of the discrete-time cellular neural network for a prescribed binary image processing problem are calculated. Application examples including edge detection, connected component detection, and hole filling are given to demonstrate the merits and limitations of the proposed method. For a given realization of the parameters of the cloning template, a guideline for the selection of the offset Ic for maximum error tolerance is also considered.

The paper considers multiple-valued logic systems having the property that the ambiguity of the system increases as the ambiguity of each component increases. The partial-ordering relation with respect to ambiguity with the greatest element 1/2 and minimal elements 0, 1 or simply the ambiguity relation is introduced in the set of truth values V {0, 1/ (p1), , 1/2, , (p2) / (p1), 1}. A-monotonic p-valued logic functions are defined as p-valued logic functions monotonic with respect to the ambiguity relation. A necessary and sufficient condition for A-monotonic p-valued logic functions is presented along with the proofs, and their logic formulae using unary operators defined in the ambiguity relation are given. Some discussions on the extension of theories to other partial-ordering relations are also given.

Design of locally computable combinational circuits is a very important subject to implement high-speed compact arithmetic and logic circuits in VLSI systems. This paper describes a multiple-valued code assignment algorithm for the locally computable combinational circuits, when a functional specification for a unary operation is given by the mapping relationship between input and output symbols. Partition theory usually used in the design of sequential circuits is effectively employed for the fast search for the code assignment problem. Based on the partition theory, mathematical foundation is derived for the locally computable circuit design. Moreover, for permutation operations, we propose an efficient code assignment algorithm based on closed chain sets to reduce the number of combinations in search procedure. Some examples are shown to demonstrate the usefulness of the algorithm.

An idea of optimal output permutation of multiple-valued sum-of-products expressions is presented. The sum-of-products involve the TSUM operator on the MIN of window literal functions. Some bounds on the maximum number of implicants needed to cover an output permuted function are clarified. One-variable output permuted functions require at most p1 implicants in their minimal sum-of-products expressions, where p is the radix. Two-variable functions with radix between three and six are analyzed. Some speculations of maximum number of the implicants could be established for functions with higher radix and more than 2-variables. The result of computer simulation shows that we can have a saving of approximately 15% on the average using permuting output values. Moreover, we demonstrate the output permutation based on the output density as a simpler method. For the permutation, some speculation is shown and the computer simulation shows a saving of approximately 10% on the average.

This paper presents Bi-CMOS current-mode multiple valued logic circuit with 1.5 V supply voltage. This circuit is composed of current mirror, threshold detector and current source. This circuit has advantages such as high accuracy, high speed, high density and low supply voltage. So, it is possible to realize high-radix multiple valued logic circuit. As an other application of the proposed circuit, a processing unit of fuzzy inference is given. This circuit operates with high speed and high accuracy. The circuit simulation of the proposed circuit has been performed using SPICE2 program.

Various models of a neuron have been proposed and many studies about them and their networks have been reported. Among these neurons, this paper describes a study about the model of a neuron providing its own feedback input and possesing a chaotic dynamics. Using a return map or a histogram of laminar length, type-I intermittency is recognized in a recurrent neuron and its network. A posibility of controlling dynamics in recurrent neural networks is also mentioned a little in this paper.

This paper proposes a feedback-loop type transmission power control (TPC) scheme coupled with first and second order prediction methods and analyzes the optimum control period and residual control error. In order to minimize residual control error, the three main factors contributing to residual control error are analyzed. First, to detect accurately up-link rain attenuation, a channel quality detection method is proposed and analyzed experimentally for puseudo-error detection. Second, rain attenuation rates in Ka band are measured and analyzed statistically. Finally, the optimum control period of the proposed TPC scheme is analyzed. The simulation results on the prototype TPC system show a maximum of 4.5 dB residual control error is achievable with an optimum control period of about 1 second to 1.5 seconds.

With increases in frequency and density of RISC microprocessors due to rapid advances in architecture, circuit and fine device technologies, power consumption becomes a bigger concern. Supply voltage should be reduced from 5 V to 3.3 V. In this paper, several novel circuits using 0.5µm BiCMOS technology are proposed. These can be applied to a superscalar RISC microprocessor at 3.3 V power supply or below. High speed and low power consumption characteristics are achieved in a floating-point data path, an integer data path and a TLB by using the proposed circuits. The three concepts behind the proposed high speed circuit techniques at low voltage are summarized as follows. There are a number of heavy load paths in a microprocessor, and these become critical paths under low voltage conditions. To achieve high speed characteristics under heavy load conditions without increasing circuit area, low voltage swing operation of a circuit is effective. By exploiting the high conductance of a bipolar transistor, instead of using an MOS transistor, low swing operation can be got. This first concept is applied to a single-ended common-base sense circuit with low swing data lines in the register file of a floating and an integer data path. Both multi-series transistor connections and voltage drops by Vth of MOS transistors and Vbe of bipolar transistors also degrade the speed performance of a circuit. Then the second concept employed is a wired-OR logic circuit technique using bipolar transistors which is applied to a comparator in the TLB instead of multi-series transistor connections of CMOS circuits. The third concept to overcome the voltage drops by Vth and Vbe is addition of a pull up PMOS to both the path logic adder and the BiNMOS logic gate to ensure the circuits have full swing operation.

Under the conditions of Poisson arrivals and single copy transmission, we designed a minimum delay protocol for packet satellite communications. The approach is to assume a hybrid random-access/reservation protocol, derive its average delay and minimize the delay with respect to all tunable system parameters. We found that for minimum average delay,1) a spare reservation should normally but not always be made for each packet transmission.2) all unreserved slots (i.e. Aloha slots) should be filled with a packet rate of one per slot whenever possible. In other words, the utilization of Aloha slots should be maximized.3) an optimum balance between transmitting packets and making reservations before transmission should be maintained.

Process and device technologies of CMOS devices for low-voltage operation are described. First, optimum power-supply voltage for CMOS devices is examined in detail from the viewpoints of circuit performance, device reliability and power dissipation. As a result, it is confirmed that power-supply voltage can be reduced without any speed loss of the CMOS device. Based upon theoretical understanding, the author suggests that lowering threshold voltage and reduction of junction capacitance are indispensable for CMOS devices with low-voltage supply, in order to improve the circuit performance, as expected from MOS device scaling. Process and device technologies such as Silicon On Insulator (SOI) device, low-temperature operation and CMOS Shallow Junction Well FET (CMOS-SJET) structure are reviewed for reduction of the threshold voltage and junction capacitance which lead to high-seed operation of the COMS device at low-voltage.

This paper proposes a suitable combination of the digital modulation schemes and the coding-rate of forward error correction (FEC) schemes for satellite digital video communication networks. The comparative study is carried out by computer simulation considering non-linearly amplified, narrow bandwidth satellite channels with adjacent channel interference signals. The proposed system employs an offset QPSK modulation scheme supported by the coding-rate of 7/8 convolutional encoding and Viterbi decoding to realize high-quality and compact spectrum characteristics in non-linear channels. By employing a 32Mbps DPCM video codec, the developed prototype system achieves a post demodulated S/N ratio of higher than 52dB. Moreover, it achieves high protection ratio against co-channel interference than conventional analog FM systems. The optimized digital video transmission system makes it possible to transmit high-quality NTSC video signals over non-linearly amplified narrow bandwidth satellite channels, for example 27MHz or 36MHz bandwidth transponders, with high-security digital encryption.

In this paper, we are concerned with a problem of obtaining an approximate solution of a finite-dimensional nonlinear equation with guaranteed accuracy. Assuming that an approximate solution of a nonlinear equation is already calculated by a certain numerical method, we present computable conditions to validate whether there exists an exact solution in a neighborhood of this approximate solution or not. In order to check such conditions by computers, we present a method using rational arithmetic. In this method, both the effects of the truncation errors and the rounding errors of numerical computation are taken into consideration. Moreover, based on rational arithmetic we propose a new modified Newton interation to obtain an improved approximate solution with desired accuracy.

This paper addresses onboard processing architecture employing direct regeneration. The advantage of direct regeneration is its hardware simplicity, even though the bit error rate performance is slightly inferior to that of demodulation-remodulation scheme with coherent detection. The channel filtering schemes as well as achievable capacities are examined by computer simulation. It is found that the system with direct regeneration has advantage in channel capacity and transmit earth station e.i.r.p. for small earth stations. A possible configuration of direct regeneration onboard in future satellite systems is proposed.