Many practical communication protocols provide priority service as well as ordinary service. In such a protocol, the protocol machines can initiate a priority service at most of the states. This characteristic leads an extreme increment of the number of state transitions on the protocol machines and causes state space explosion in verification of safety property of the protocol. This paper describes a method of constructing a communication protocol from composition of a subprotocol for ordinary service and that for priority service. This paper also presents a sufficient condition for a composed protocol to inherit safety property from the subprotocols. By using the composition method and the sufficient condition, the decision problem for safety property of the composed protocol can be reduced to those of the subprotocols. An experimental result of verification of a part of OSI session protocol is also described. The result shows that the method can reduce the computation time for verifying safety property to about 3% against the naive way.

This paper describes the architecture and the performances of a GaAs 88 self-routing switch LSI for ATM switching system. The communication system such as broadband integrated sevices digital network (B-ISDN) requires the hardware switch LSI which exchanges packet cells at a date rate up to several Gb/s. GaAs LSIs are suitable for such application because of its high speed operation and low power dissipation. To clarify the feasibility of GaAs LSI, an 88 self-routing switch LSI is fabricated using 0.5 µm gate GaAs MESFETs and its oerformances are examined. This LSI consists of a switching network for exchanging the packet cells and the "NEMAWASHI" network which detects the cell destined to the same output port. The basic network architecture is a self-routing switch using Batcher-Banyan network. This network consists of basic 22 switch element. Since each element switches the route accorging to the destination of the input cells, self-routing operation is performed without the external circuit for routing control. The LSI is fabricated using 0.5 µm gate GaAs MESFETs. 7003 logic gate are integrated on the chip of 8.2 mm7.4 mm. To reduce the impedance of ground line on the chip and to obtain the enough noise margin, the third level interconnection with low sheet resistance is implemented. As the results of functional evalution, the full function of switching network and "NEMAWASHI" network are verified. Maximum operation speed of 1 GHz is obtained.

OGIS Research Institute and Osaka Gas have developed two intelligent tutoring systems (ITSs): PCTS (Process Control Training System) and PDTS (Power Distribution Training System). This paper describes a basic concept of an ITS for plant operation based on the experience of their development. The topics include: (1) The features and structure of PCTS (i.e., text based training and model based training, a simulation model based on OOP, an intelligent authoring system). (2) What kinds of stages are needed for training systems from the view point of cognitive science (i.e., verbal learning multiple discrimination learning, rule learning, compound rule learning problem solving). (3) How to detect trainees' missing operational steps and misoperations using the perturbation method.

The throughput of a parallel execution of a Digital Signal Processing (DSP) algorithm is limited by the iteration bound, which is the minimum period between the start of consecutive iterations. It is given by T=max (Ti/Di), where Ti and Di are the total time of operations and the number of delays in loop i, respectively. A schedule is said rate-optimal if its iteration period is T. The throughput of a DSP algorithm execution can be increased by reducing the Ti's, which can be done by taking as many operations as possible out of loops without changing the semantic of the calculation. This paper presents an optimization technique, called Loop Shrinking, which reduces the iteration bound this way by using commutativity, associativity and distributivity. Also, this paper presents a scheduling method, called Period-Driven Scheduling, which gives rate-optimal schedules more efficiently than existing approaches. An implementation of both is then presented for a system in development by the authors. The system shows reduction in the iteration bound near or equal to careful hand-tunning, and hardware-optimal designs in most of the cases.

This paper presents an efficient heuristic algorithm for min-cut bisection of weighted hypergraphs. The proposed algorithm is based on a heuristic algorithm proposed by Kahng, which was devised for non-weighted hypergraph bisection, adopting a non-weighted graph called intersection graph to represent a given hypergraph. In the proposed algorithm, instead of an intersection graph, a bipartite graph called netgraph is newly introduced to explicitly represent the weights of nodes of a hypergraph. Using the netgraph, it is easy to partition a weighted hypergraph into two hypergraphs with same size. Computation time of the proposed method is O(m2), where m is the number of nodes of a given hypergraph. Experimental results with real circuit data show that the proposed method produces better solutions in shorter computation time compared with existing methods.

This paper deals with the sub-problems of generating a mask pattern from the logical description of a large-scale CMOS circuit. The large-scale layout can be generated in divide-and-conquer style: divide a given circuit into a set of sub-circuits, generate the layout of each sub-circuit, and merge the resulting layouts to create the whole layout. This paper proposes a layout synthesis algorithm for a sub-circuit with physical constraints for the synthesis scheme above. The physical constraints considered here are the relative placement of logic cells (sets of logic gates) and the routing constraint based on the costs of wiring layers and vias. These constraints will be given by the global optimizer in a two-dimensional layout synthesis routine, and they should be kept at the subsequent one-dimensional layout synthesis for a sub-circuit. The latter is also given for enhancing the circuit performance by limiting the usage of wiring layers and vias for special net such as a clock net. The placement constraint is maintained using PQ-tree, a tree structure representing a set of restricted permutations of elements. One-dimensional layout synthesis determines the placement of transistors by the enhanced pairwise exchanging method under the PQ-tree representation. The routing constraints is considered in the newly developed line-search routing method using a cost-based searching. Experimental results for practical standard cells, including up to 200 transistors, prove that the algorithms can produce the layouts comparable to handcrafted cells. Also on a two-dimensional layout synthesis using the algorithms, the results for benchmark circuits of Physical Design Workshop 1989, i.e., MCNC benchmark circuits, are superior to the best results exhibited at Design Automation Conference 1990.

This paper describes a modeling of the cryptography based on a concept of Petri nets. Movement of tokens in the net model shows a dynamic behavior of systems. On the other hand, the cryptography is considered as a bit operation, so that we can point out a common property between the net structure and the cryptography, which provides our idea that movement of tokens of the net model corresponds to a bitoperation of the cryptography. Some effective keys in the net model are considered by means of the net elements, which are based on T-invariant and net structures. It is shown that the keys of the net structured cryptography provide reasonable strength comparing with the data encryption standard (DES).

An automatic macrocell generator has been developed and applied to the analog layout of SC and active-RC filters. The generator consists of a process independent generation procedure, a leafcell library, and a circuit description of the leafcells. The unit element arrays of the whole filter are generated together to minimize the array height of the entire filter macrocell, so that the area of the generated filter is as small as that of a manually laid out filter. Three SC filters and one active-RC filter were designed and fabricated by 1.5-µm CMOS technology, that successfully yielded an S/N ratio of more than 70 dB with a quick turn around time.

Net-Oriented Analysis and Design (NOAD) is defined as three items: (1) Various nets are utilized as an effective modeling method. (2) Inter-relationships among verious nets are determined. (3) Verification or analysis methods for nets are provided and they are implemented based on the mathematical theory, that is Net theory. Very few methods have been presented to satisfy these three items. For example, the Real-Time SA method covers item (1) only. The Object-Oriented Analysis and Design method (OOA/OOD) covers items (1) and (2). NOAD can be regarded as an extension to OOA/OOD. This paper discusses how effectively various nets have been used in actual software development support metnods and tools and evaluates such several methods and tools from the NOAD viewpoint.

An autonatic layout scheme dedicated to bipolar analog modules is described. A layout model is settled in such a way that the VCC/GND line is laid out on top/bottom edge of a rectangular region, within which the whole elements are placed and interconnected. According to this simple modeling, a layout scheme can be constructed of a series of the following algorithms: First clustering is executed for partitioning a given circuit into clusters, each having connections with VCC and GND lines, and then linear ordering is applied to clusters so as to be placed in a one-dimensional array. After a relative placement of circuits elements in each cluster, a block compactor is implemented by means of packing blocks in each cluster into an idle space, and then a detailed router is conducted to attain 100% interconnection. Finally a layout compactor is invoked to pack all layout patterns into a rectangle of the minimum possible area. A number of implementation results are also shown to reveal the practicability of the proposed analog module generator.

This paper presents a protocol verification method which verifies that the behaviors of a protocol meet requirements. In this method, a protocol specification is expressed as Extended Finite State Machines (EFSM's) that can handle variables, and requirements are expressed using a branching-time temporal logic for a concise and unambiguous description. Using the acyclic expansion algorithm extended such that it can deal with EFSM's, the verification method first generates a state transition graph consisting of executable transitions for each process. Then a branching-time temporal logic formula representing a requirement is evaluated on one of the generated graphs which is relevant to the requirement. An executable state transition graph for each process is much smaller than a global state transition graph which has been used in the conventional verification techniques to represent the behaviors of the whole protocol system consisting of all processes. The computation for generating the graphs is also reduced to much extent for a large complex protocol. As a result, the presented method achieves efficient verification for requirements regarding a state of a process, transmission and reception of messages by a process, varibales of a process and sequences that interact among processes. The validity of the method is illustrated in the paper by the verification of a path-updating protocol for requirements such as process state reachability or fair termination among processes.

In most of the methods proposed so far to design approximately linear phase IIR digital filters (IIR DFs), the design takes place only in the time or in the frequency domain. However, when both magnitude and phase responses are considered, IIR DFs with better frequency responses can be obtained if their characteristics in both domains are taken into account. This paper proposes a design method for approximately linear phase IIR DFs, which is based on parameter estimation techniques in the time domain followed by a nonlinear optimization algorithm in the frequency domain. Several examples are presented, illustrating the proposed method.

In this paper, the software structure for telecommunication user support are discussed, and it is proposed to apply knowledge processing technology to the software. Capabilities of telecommunications networks are becoming quite complicated, and the number of service items and parameters which have to be selected and memorized will become too large for telecommunications end users to make full use of the network capabilities. As such, more effort should be focused on assisting telecommunications end users to use the network and providing user friendly human interfaces of the network. However, this kind of software has additional type of requirements other than those for protocol handling software and call control software, and the realization of such support software has not yet been fully studied. To realize such support software, this paper stressed the realization of the user-system interface. Especially identified in this paper are meaning-based interpretation of user inputs to permit the handling of synonyms and multivocations, and a method to access the database in the support system without consideration of its data schema. To satisfy these objectives, this paper has proposed that the application data should be represented in both a character string and a meaning representation, and that the thesauruses should have the attribute-value relation. In line with these studies, an experimental system called CAPRIS (CAlling PRocedure Instruction System) was developed. It is used to assist the calling party in a telecommunications network to find an appropriate contact point depending on the purpose of the communication. Implementation of CAPRIS is completed and it was confirmed that all the functions described in this paper were actually realized. Some functional experiments were performed on CAPRIS, and the system was concluded to realize satisfactory user-friendliness.

The pursuit of higher availability has resulted in the development of fault tolerant systems for many industries. However, system characteristics that can be perceived by the customer have never been diagnosed quantitatively. This paper considers the application of stochastic Petri nets with general firing times to modeling of a fault tolerant system and the use of discrete-event simulation methods for stochastic Petri nets to study the behavior of the system. The stochastic Petri net model incorporates factors that compose the system as well as those that accompany it, including RAS characteristics of products, personnel arrangements, and system management. By modeling the behavioral aspect of each factor, it is possible to diagnose a fault tolerant system quantitatively on the basis of customer impact.

The subject of the paper is the minimum initial marking problem for scheduling in timed Petri net PN: given a vector X of nonnegative integers, a P-invariant Y of PN and a nonnegative integer π, find an initial marking M minimizing the value YtrM among those initial marking M such that there is a scheduling σ having the total completion time τ(σ)π with respect M , X and PN (a sequence of transitions, with the first transition firable on M , such that every transition t can fire prescribed number X(t) of times). The paper shows NP-hardness of the problem and proposes two approximation algorithms with their experimental evaluation.

Recent trends in down-sizing have resulted in the development of client server systems for many industries. This paper considers the application of stochastic Petri nets with general firing times for modeling of a concatenated client server system and the use of discrete-event simulation methods for stochastic Petri nets to study its behavior. This approach enables us to assess the most appropriate resource set of a concatenated client server system on the quantitative basis of the performability and the occurrence of system down conditions. Thus, system consultation, a new application of stochastic Petri nets, is presented.

We developed a 32-bit pseudorandom number generator (RNG) operating at liquid nitrogen temperature based on HEMT ICs. It generates maximum-length-sequence codes whose primitive polynomial is X47+X42+1 with the period of 247-1 clock cycle. We designed and fabricated three kinds of cryogenic HEMT IC for this system: A 1306-gate controller IC, a 3319-gate pseudorandom number generator (RNG) IC, and a buffer IC containing a 4-kb RAM and 514 gates. We used 0.6-µm gate-length Se-doped GaAlAs/GaAs HEMTs. Interconnects were Al for the first layer and Au/Pt/Ti for the second layer with a SiON insulator between them. The HEMT ICs have direct-coupled FET logic (DCFL) gates internally and emitter-coupled logic (ECL) compatible input-putput buffers. The unloaded basic delay of the DCFL gate was 17 ps/gate with a power consumption of 1.4 mW/gate at liquid nitrogen temperature. We used an automatic cryogenic wafer probe we developed and an IC tester for function tests, and used a high-speed performance measuring system we also developed with a bandwidth of more than 20 GHz for high-speed performance tests. Power dissipations were 3.8 W for the controller IC, 4.5 W for the RNG IC, and 3.0 W for the buffer IC. The RNG IC, the largest of the three HEMT ICs, had a maximum operating clock rate of 1.6 GHz at liquid nitrogen temperature. We submerged a specially developed zirconium ceramic printed circuit board carrying the HEMT ICs in a closed-cycle cooling system. The HEMT ICs were flip-chip-packaged on the board with bumps containing indium as the principal component. We confirmed that the RNG system operates at liquid nitrogen temperature and measured a minimum system clock period of 1.49 ns.

This paper describes a reduction algorithm for SW method which generates test sequences for communication systems. SW method is based upon the Finite State Machine (FSM). SW method uses a set of characterizing sequences and a state transition checking approach. This paper concentrates the characteristics of the SW sequences, and proposes the new derivation algorithm of characterizing sequences. Furthermore, Chinese Postman Tour and Extended Chinese Postman Tour is proposed to reduce redundancy of the SW sequences. This paper also presents an evaluation of this method in terms of an upper bound of the sequence length and generated test sequence length. The evaluation shows that the algorithm dramatically reduces the sequence length of the original method.

This paper deals with a network architecture based on a backbone network, using ATM switches (ATM-SW) and ATM Cross-Connect Systems (ATM-XC). The backbone network is efficiently utilized by multiple-routing scheme. The performance of the network is controlled, exploiting the concept of Virtual Paths (VP) in ATM technology. The network is controlled by allocating the bandwidth of VPs so as to minimize the worst call blocking probability of all ATM-SW pairs, under the constraints of the ATM-SW capacities and the bandwidths of transmission paths in the backbone network. To improve network performance, we use a trunk reservation scheme among service classes. We propose a heuristic approach to solve the problem of non-linear integer programming. Evaluation of the proposed optimization scheme, in comparison to other optimal methods, shows the efficiency of the present scheme.

The quality of polycrystalline silicon films and electrical characteristics of polycrystalline silicon gate metal-oxide-semiconductor (MOS) capacitors were investigated under various processing conditions, including phosphorus doping. The stresses observed in Si films deposited in the amorphous phase show complex behavior during thermal treatment. The stresses in as-deposited Si films are compressive. They change to tensile with annealing at 800, and to compressive after an additional annealing at 900. The kind of charges trapped in the SiO2 film during the negative constant current stress in Polycrystalline silicon gate MOS capacitors differ with the maximum process temperature. The trapped charges of samples annealed at 800 were negative, while those of samples annealed at 900 were positive.