This paper deals with the theory and design method of an efficient radix-4 divider using carry-propagation-free adders based on redundant binary {-1,0,+1} representation. The usual method of normalizing the divisor in the range [1/2,1) eliminates the advantages of using a higher radix than two, bacause many digits of the partial remainder are required to select the quotient digits. In the radix-4 case, it is shown that it is possible to select the quotient digits to refer to only the four (in the usual normalizing method it is seven) most significant digits of the partial remainder, by scaling the divisor in the range [12/8,13/8). This leads to radix-4 dividers more effective than radix-2 ones. We use the hyperstring graph representation proposed in Ref.(18) for redundant binary adders.

We propose a design method for a two-channel perfect reconstruction FIR filter banks employing linear-phase filters. This type of filter bank is especially important in splitting image signals into frequency bands for subband image cording. Because in such an application, it is necessary to use the combination of linear-phase filters and symmetric image signal, namely linear phase signal to avoid the increase in image size caused by filtering. In this paper, first we summarize the design conditions for two-channel filter banks. Next, we show that the design problem is reduced to a very simple linear equation, by using a half-band filter as a lowpass filter. Also the proposed method is available to lead filters with fewer complexity, which enable us to use simple arithmetic operations. For subband coding, the property is important because it reduces hardware complexity.

Formal verification has become an increasing prominent technique towards establishing the correctness of hardware designs. We present a framework to specifying and verifying the design of systolic architectures. Our approach allows users to represent systolic arrays in Z specification language and to justify the design semi-automatically using the verifier. Z is a notation based on typed set theory and enriched by a schema calculus. We describe how a systolic array for matrix-vector multiplication can be specified and justified with respect to its algorithm.

This paper describes a novel but simple method of implementing waveform relaxation technique for bipolar circuits involving ECL gates. This method performs gate level partitioning of ECL circuits not only during the cutoff state of the input transistor but also when the input transistor is in its active state. Partitioning at all times has become possible due to the favorable property of input and output stages of ECL gates. It is shown that this method is faster than direct method even when the circuits containing only few gates is simulated. Further, it is shown that the present method is applicable to the case where the interconnections between the ECL gates is treated as lossy transmission lines.

This paper describes the novel relaxation-based algorithm for the harmonic analysis of nonlinear circuits. First, we present Iterated Spectrum Analysis based on harmonic balance method, where the harmonic balance method is applied to every node independently. As a result, we can avoid dealing with large scale Jacobian matrices and reduce the total simulation time, compared with the conventional method based on Galerkin's procedure or the harmonic balance method. Next, we define the frequency domain latency. Furthermore, we refer to the possibility for exploitation of three types of latency, i.e., relaxation iteration latency, frequency domain latency and Newton iteration latency. And we propose the multirate-sampling technique based on the consideration of the frequency domain latency. Finally, we apply the present technique to the simple analog circuit simulation and verify its availability for the harmonic analysis.

Gradient-based methods for the computation of the velocity from image sequences assume that the velocity field varies smoothly over image. This creates difficulties at regions where the image intensity changes abruptly such as the occluding contours or region boundaries. In this letter, we propose a method to overcome these difficulties by incorporating the information of discontinuities in image intensity into a standard local optimization method. The presented method is applied to the synthetic and real images. The results show that the velocity field computed by the proposed method is less blurred at region boundaries than that of the standard method.

The minimum transferable linewidth by X-ray is derived using waveguide analysis. The minimum width is determined by the refractive index of the absorber and does not depend on the X-ray wavelength. Therefore there is an optimum mask aperture size which provides the minimum linewidth. By using Au as the absorber, 8 nm linewidth is attainable.

The concentration of the electric field at the edge of the electrode has been simulated in several types of flat DRAM cell capacitors with high permittivity dielectrics. The results indicated that the permittivity of the material surrounding the edge of the electrode as well as the geometrical structure affected the concentration of the electric field. The electric field strength was minimized and most evenly distributed by utilizing the structure in which the sidewall of the capacitor dielectric was terminated at the edge of the electrode by a low-dielectric constant insulator. High-precision fabrication of the capacitor's profile is required for the minimization and uniformity of the electric field.

Correspondence based on regions rather than lines seems to be effective, as regions are usually fewer than other image features and provide global information such as size, color, adjacency, etc. In this paper, we present a region matching approach for solving the correspondence problem. Images are segmented into regions and are individually described by classification tables using region adjacencies. From the structural description of the two images, the region matching process based on color and structural similarity is carried out. First, a small number of significant regions are selected and matched by using color, and then they are used as handles for constraint propagation to match the remaining regions by using structures. Our technique was implemented by using an efficient selection and propagation algorithm and was tested with a variety of scenes.

This paper proposes an off-line text-independent writer identification method applicable to Japanese and Korean sentences. It is assumed that the writer of a writing in question exists in a certain group of people and that reference writings written by each person in the group can be used for identification. In the proposed method, relative frequencies of some model patterns are counted on the binary pattern of each writing and are used as the feature to measure the distance between two writings. Based on a modified Mahalanobis' distance for this feature, the person whose reference writing is nearest to the writing in question is judged as the writer. The effectiveness of the proposed method is examined through an experiment using Japanese and Korean writings. Error rates in the experiment were different depending on conditions such as volume of reference writings, dimension of adopted features, and number of people to be identified. In some cases, error rates as low as 0% were observed. Error rates tend to be lower in Korean writings probably because Hangul is composed of a smaller number of letters compared to Kanji and Hiragana in Japanese writing.

Mathematical morphology clarified geometrical properties of shape analysis algorithms for binary pictures. Results of labelling, distance transform, and adjacent numbering are, however, coded pictures. For full descriptions of shape analysis algorithms in the framework of mathematical morphology, it is necessary to extend morphological operations to code-labelled pictorial data. Nevertheless, extensions of morphology to code-labelled pictures have never discussed though the theory of gray morphology is well studied by several authors. Hence, this paper proposes a theory of the coded morphology which is based on the binary scaling of labels of pixels. The method uses n-layered binary sub-pictures for the processing of a picture with 2n labels. By introducing morphological operations for the coded point sets, we express some coding functions in the manner of the mathematical morphology. We also derive multidimensional array registers and gates which store and process coded pictures and morphological operations to them by proposing basic gates which compute parallelly logical operations for elements of Boolean layered arrays. These gates and registers are suitable for the implementation of the shape analysis processors on the three-dimensional VLSI and ULSI.

The 22 mechanical optical switch for single mode fiber (SMF) is reported. By using the precision grinding and molding techniques all-plastic multiple-fiber connector, 22 pin-referenced indirect slide switch is developed. The characteristics and the reliability test's results of this optical switch are also reported. Evaluations confirm that the switch has low insertion loss, high-speed switching, stable switching operations and reliability in practical applications.

Two kinds of nitrided ultrathin (510 nm) SiO2 films were formed on the silicon (100) face using rapid thermal NH3-nitridation (RTN) and rapid thermal N2O-oxynitridation (RTON) technologies. The MOS capacitors with RTN SiO2 film showed that by Fowler-Nordheim (F-N) electron injection, both electron trap density and low-field leakage increase by the NH3-nitridation. In addition, the charge-to-breakdown (QBD) value decreases owing to NH3-nitridation. By contrast, RTON SiO2 films exhibited extremely low electron trap density, almost no increase of the leakage current, and large QBD value above 200C/cm2. The oxide film composition was evaluated by secondary ion mass spectroscopy (SIMS). The chemical bonding states were also examined by Fourier transform-infrared reflection attenuated total reflectance (FT-IR ATR) and X-ray photoelectron spectroscopy (XPS) measurements. These results indicate that although a large number of nitrogen (N) atoms are incorporated by the RTN and RTON, only the RTN process generates the hydrogen-related species such as NH and SiH bounds in the film, whereas the RTON film indicates only SiN bonds in bulk SiO2. From the dielectric and physical properties of the oxide films, it is considered that the oxide wearout by high-field stress is the result of the electron trapping process, in which anomalous leakage due to trap-assisted tunneling near the injected interface rapidly increases, leading to irreversible oxide failure.

Phosphorus-doped amorphous or polycrystalline silicon can yield a conformal, low resistance, thermallystable plug for the high-aspect-ratio, sub-half-micron contactholes found in current development prototypes of future 64 and 256 Mega-bit DRAMs. When directly contacted to a silicide layer, however, such as WSix found in polycide gate or bit line metallization/contact structures, the outdiffusion of phosphorus from the doped-silicon layer into the silicide can occur, resulting in an increase in resistance. The characteristics of both the doped-silicon and WSix layers influence the outdiffusion. The grain size of the doped silicon appears to control diffusion at the WSix/doped-silicon interface while the transition of WSix from an as-deposited amorphous to a post-annealed polycrystalline state appears to help cause uniform phosphorus diffusion throughout the silicide film. The results of phosphorus pre-doping of the silicide to reduce the effects of outdiffusion are dependent upon the relative material volumes and interfacial areas of the layers. Due to the effectiveness of the TiN barrier layer/Ti contact layer structure used in Al-based contacts, Ti and TiN were evaluated on their ability to prevent phosphorus outdiffusion. Ti reacts easily with doped silicon and to some extent with WSix, thereby allowing phosphorus to outdiffuse through the TiSix into the overlying WSix. TiN, however, is very effective in preventing phosphorus outdiffusion and preserving polycide interface smoothness. A WSix/TiN/Ti metallization layer on an in situ-doped (ISD) silicon layer with ISD silicon-plugged contactholes yields contact resistances comparable to P+-implanted or non-implanted WSix layers on similar ISD layers/plugs for contact sizes greater than approximately 0.5 µm but for contacts of 0.4 µm or below the trend in contact resistance is lowest for the polycide with TiN barrier/Ti contact interlayers. A 20 nm-thick TiN film retains its barrier characteristics even after a 4-hour 850 anneal and is applicable to the silicide-on-doped-silicon structures of future DRAM and other ULSI devices.

A new capacitor over bit-line (COB) stacked capacitor memory cell was developed using a local interconnect poly-silicon layer to arrange a capacitor contact between bit-lines. This memory cell enables usable capacitor area to increase and capacitor contact hole depth to decrease. The hemispherical grain (HSG) silicon, whose effective surface area is twice that of ordinary poly-silicon, was utilized for the storage node to increase the storage capacitance without increasing the storage node height. The feasibility of achieving a 1.8 µm2 memory cell with 30 fF storage capacitance using a 7 nm-SiO2-equivalent dielectric film and a 0.5 µm-high HSG storage node has been verified for 64 MbDRAMs by a test memory device using a 0.4 µm CMOS process.

A new technique for evaluating gate oxide reliability using photon emission method has been developed. This method enables the measurements of the initial breakdown characteristics, reliability testing and failure analysis consistently. From the experimental results, followings are clarified for the first time using this technique. Failure modes in the initial characteristics have close correlation to TDDB characteristics and both characteristics correspond to the location of breakdown spot. The results suggest measures to improve the reliability of gate oxide and the existance of new failure mechanism.

A novel CMOS structure has been developed using Ti-salicide PSD transistor formed by a new self-aligned method. Both N-channel and P-channel PSD transistors exhibit excellent short-channel behaviors down to the sub-half-micrometer region with shallow S/D junctions formed by dopant diffusion from polysilicons. New salicide process has been developed for the PSD structure and can effectively reduce the sheet resistances of the S/D polysilicon and the polysilicon gate to as low as 45Ω/. As a result, the low resistive local interconnects can be successfully implemented by the Ti-salicide S/D polysilicon merged with contacts by self-alignment. More-over it is found that shallow Ti-salicide S/D junctions with the PSD structure can achieve approximately 12 orders of magnitude lower area leakage current than that of the conventional implanted S/D junctions by eliminating implanted damage and preventing penetration of silicide into junctions with the elevated structure of S/D polysilicon layer. Furthermore CMOS ring oscillators having PSD transistors with an effective channel length of 0.4 µm were fabricated using the salicided S/D polysilicon as a local interconnect between the N+ and the P+ regions, and successfully operated with a propagation delay time of 50 ps/stage at a supply voltage of 5 V.

Optical soliton transmissions at 10 and 20Gbit/s over 1000km with the use of erbium-doped fiber amplifiers are described in detail. For the 10Gbit/s experiment, a bit error rate (BER) of below 110-13 was obtained with 220-1 pseudorandom patterns and the power penalty was less than 0.1dB. In the 20Gbit/s experiment optical multiplexing and demultiplexing techniques were used and a BER of below 110-12 was obtained with 223-1 pseudorandom patterns under a penalty-free condition. A new technique for sending soliton pulses over ultralong distances is presented which incorporates synchronous shaping and retiming using a high speed optical modulator. Some experimental results over 1 million km at 7.210Gbit/s are described. This technique enables us to overcome the Gordon-Haus limit, the accumulation of amplified spontaneous emission (ASE), and the effect of interaction forces between adjacent solitons. It is also shown by computer runs and a simple analysis that a one hundred million km soliton transmission is possible by means of soliton transmission controls in the time and frequency domains. This means that limit-free transmission is possible.

The path diversity improvement inherent in direct sequence spread spectrum (DS/SS) signalling under multi-path propagation environments is investigated for mobile/personal radio communications systems that employ DPSK modulation. The bit error rate (BER) performance of post-demodulation selection diversity reception is theoretically analyzed in the presence of noise-only-paths in the time window for diversity combining. Results of laboratory experiments conducted to evaluate the BER performance are also presented. It is shown that the experimental results agree well with the theoretical BER.

Copper contamination behavior is studied, depending on the pH level, conductivity type P or N of a silicon substrate, and contamination method of copper. If the pH level of a copper containing solution is adjusted by using ammonia, copper atoms and ammonia molecules produce copper ion complexes. Accordingly, the amount of copper adsorption on the substrate surface is decreased. When N-type silicon substrates are contaminated by means of copper containing solutions, copper atoms on the surfaces diffuse into bulk crystal even at room temperature. But for P-type silicon substrates, copper atoms are transferred into bulk crystal only after high temperature annealing. In the case of silicon substrates contaminated by contact with metallic copper, no copper atom diffusion into bulk crystal was observed. The above mentioned copper contamination behavior can be explained by the charge transfer interaction of copper atoms with silicon substrates.