Optical recording has been performed successfully by the preirradiation of light upon the precursor of poly (arylene vinylene) conducting polymers such as poly (p-phenylene vinylene) (PPV) and poly (1,4-naphthalene vinylene) (PNV) and subsequent thermal treatment. The effect has been tentatively interpreted in terms of the deterioration of the irradiated area of the precursor polymer in which polymerization is suppressed. Furthermore, an orange electroluminescent (EL) diode utilizing PNV has been demonstrated for the first time and the EL properties of PNV are discussed in comparison with those of EL diode utilizing PPV. The EL emission of these two devices are discussed in terms of radiative recombination of the singlet polaron exciton formed by the injection of electrons and holes, the difference of effective conjugation length and the interchain transfer of polaron excitons.

A novel pulse neural network model for sound localization has been proposed. Our model is based on the physiological auditory nervous system. Human beings can perceive the sound direction using inter-aural time difference (ILD) and inter-aural level difference (ILD) of two sounds. The model extracts these features using only pulse train information. The model is divided roughly into three sections: preprocessing for input signals; transforming continuous signals to pulse trains; and extracting features. The last section consists of two parts: ITD extractor and ILD extractor. Both extractors are implemented using a pulse neuron model. They have the same network structure, differing only in terms of parameters and arrangements of the pulse neuron model. The pulse neuron model receives pulse trains and outputs a pulse train. Because the pulses have only simple informations, their data structures are very simple and clear. Thus, a strict design is not required for the implementation of the model. These advantages are profitable for realizing this model by hardware. A computer simulation has demonstrated that time and level differences between two signals have been successfully extracted by the model.

The timing jitter reductions with differently shaped optical bandpass filters are discussed and the transmission distance achievable against the timing jitter is evaluated using optical bandpass filters in several tens of Gb/s soliton transmission. Experimental confirmation of timing jitter reduction with optical bandpass filters is demonstrated in 10Gb/s optical soliton recirculating loop experiments by measuring the timing jitter and the bit error rates.

It has been 15 years since we started producing the electric double-layer capacitors (also known as Super Capacitor) in 1978. Over the years we have introduced improvements that increased reliability and increased life. For example, after subjecting capacitors manufactured in 1984 and 1990 to load life tests (70, 5.5 V) for 2,000 hours, we discovered that the rate of change in capacitance (ΔC/C) of capacitors manufactured in 1990 was less than one-half that of capacitors manufactured in 1984. This shows that we have successfully increased the life of our electric double-layer capacitors. We conducted investigations regarding factors that contribute to volume of the electrolyte solution and better sealing properties. In the load life test, we observed that when the ratio of the weights of the electrolyte solution and the powdered activated carbon (hereinafter referred to as LB) was increased, the time it took before ΔC/C reached -30% was lengthened. This means that increasing LB also increases life. Furthermore, we also observed that when the gas permeability rate of the collector's rubber material was decreased in the load life test (70, 5.5 V), the time it took befor (ΔC/C) reached -30% was longer. Therefore life is dependent on the gas permeability rate (sealing property) of the collector rubber.

This paper describes the effective countermeasures for exfoliation of large-sized ceramic capacitors, deterioration of dummy resistors and developement of a spark sensor with UVtrons at 300-500 kW transmitting stations. Cracks and exfoliation were found at the electrode of large-sized ceramic capacitors in the output circuit of the 500 kW transmitter. The exfoliation was caused by the temperature rise and the thermal fatigues at the electrode with the Nickel plating including Irons. A pure Nickel-plated electrode including no Irons and a new soldering method using disk-typed solder with a large adhesive area are employed in order to reduce the temperature rise. The temperature rise of the improved capacitor was 18 lower than the conventional one. Deterioration of ELEMA resistors of the 300 kW dummy antenna was discovered. The damage of the resistor was caused by the concentration of the electric current followed by the thermal stress cycle which made mechanical exhaustion at the electrode. Therefore, oval-shaped type resistors with much longer electric current path (20% up) to suppress the concentration of current flow and much slower temperature rise are newly developed. In case that sparks occurred at DC or RF high voltage impressed sections of the high power transmitting equipment, the discharged points could be seriously damaged by the transmitter energy itself. In orded to prevent this, a spark detector using UV (Ultra violet) trons is developed and installed at the matchign circuit of the 500 kW transmitter. Conventional UV sensors with only one UVtron could not detect feeble discharges and sparks with a duration time of less than 150 ms because of false outputs by the back ground noise. Since choosing three out of four UV trons system is employed, possibility producing a false output will be just one to 445 years theoretically. This means extremely reliable and sensitive spark detection system are constructed. These countermeasures have improved reliability of the transmitting equipment greatly. No damages have been found in the transmitters ever since.

This paper proposes an optimal free-sensors allocation problem (OFSAP) in safety monitoring systems. OFSAP is the problem of deciding the optimal allocation of several sensors, which we call free sensors, to plural objects. The solution of OFSAP gives the optimal allocation which minimizes expected losses caused by failed dangerous (FD)-failures and failed safe (FS)-failures; a FD-failure is to fail to generate an alarm for unsafe object and a FS-failure is to generate an alarm for safe object. We show an unexpected result that a safer object should be monitored by more sensors under certain conditions.

In 1963, the authors began to develop a tuning circuit (hereafter referred to as the 'circuit') consisting of an inductor, fixed capacitors and a variable capacitor. The circuit required very high accuracy and stability, and the aging influence on resonant frequency needed to be Δf/f0 0.12% for 20 years. When we started, there was no methodology available for designing such a long-term stable circuit, so we reinvestigated our previous studies concerning aging characteristics and formed a design concept. We designed the circuit by bearing in mind that an inductor was subject to natural and stress demagnetization (as indicated by disaccommodation), and assumed that a capacitor changed its characteristics linearly over a logarithmic scale of time. (This assumption was based on short-term test results derived from previous studies.) We measured the aging characteristics of the circuits at room temperature for 20 years, from 1966. The measurement results from the 20-year study revealed that the aging characteristics predicted by the design concept were reasonably accurate.

Material research on capacitor dielectrics for DRAM applications is reviewed. The state of the art technologies to prepare Si3N4,Ta2O5, and SrTiO3 thin films for capacitors are described. The down-scaling limits for Si3N4 and Ta2O5 capacitors seem to be 3.5 and 1.5 nm SiO2 equivalent thickness, respectively. Combined with a rugged polysilicon electrode surface,Si3N4 and Ta2O5 based-capacitors are available for 256 Mbit and 1 Gbit DRAMs. At the present time, the minimum SiO2 equivalent thickness for high permittivity materials is around 1 nm with the leakage current density of 10-7 A/cm2. Among the great variety of ferroelectrics, two families of materials,i.e., Pb (Zr, Ti) O3 and (Ba, Sr) TiO3 have emerged as the most promising candidates for 1 Gbit DRAMs and beyond. If the chemical vapor deposition technology can be established for these materials, capacitor dielectrics should not be a limiting issue for Gbit DRAMs.

This letter discusses a behavior of solitons in a Josephson junction transmission line which is described by a perturbed sine-Gordon equation. It is shown that a soliton wave leads a quasi-periodic break down route to chaos in a Josephson transmission line. This route show phase locking, quasi-periodic state, chaos and hyper chaos, and these phenomena are examined by using Poincar sections, circle map, rotation number, and so on.

The Cooper pairing interaction in high Tc oxide superconductor is discussed in terms of an empirical expression; TcDexp[1/g], gcωo which was derived in our previous investigation. The dual character of this expression consisting of the phonon Debye temperature D and electronic excitation ωo in the mid-infrared region can be interpreted on the basis of the phonon-assisted mechanism on carrier conduction and the electronic excitation. A tunneling spectrum here presented shows certain evidence of the phonon contribution. The characteristics of the long range superconductive proximity phenomena recently reported are also may be interpreted by this mechanism.

This paper reviews the potential possibility and present status of trans-polyacetylene research toward realization of soliton molecular devices utilizing characteristics of the quasi-one-dimensional conductor. Properties of solitons in polyacetylene are summarized from a point of view to produce a new microelectronics beyond Si-LSI's. The limiting performance of soliton LSI's are roughly estimated. One bit information is stored in only 420 2. The information transmission rate of a wiring is 2104 Gb/s. The delay time per gate is 0.05 ps. For realization of this high performance devices, a lot of research must be carried out in future. A new circuit with new principles of operations must be developed to achieve the performance, where a localized soliton or a localized group of solitons are treated. Some systems, which may lead to development of logic circuits, are proposed. The problems in crystal quality and fabrication process are also discussed and some means against them are presented.

To improve measurement accuracy and speed, a switched-capacitor capacitance measurement circuit with the vernier scale is developed. Its process consists of a coarse measurement by charge-balancing A-D conversion and a fine measurement by single-slope A-D conversion. a prototype using discrete components confirms the principles of operation.

A cyclic analog-to-digital (A/D) converter is developed which accomplishes an n-b conversion in n/2 clock cycles. The architecture consists of two 1-b quantizers connected in a loop. A CMOS design of the 1-b quantizer is given to evaluate the performance of the A/D converter when implemented using presently available process. Spice simulations and error analyses show that a resolution higher than 10-b and a sampling rate up to 1.4 Msps are attainable with a 3-µm CMOS process. A prototype converter breadboarded using discrete components has confirmed the principles of operation and error analyses. The device count and the power consumption are small compared to those of a successive-approximation A/D converter. A chip area required for the CMOS implementation is also small because only four unit capacitors are involved. Therefore, the architecture proposed herein is most suited for high accuracy, medium speed A/D conversion.

This paper describes new methematical tools, taken from quantum field theory (QFT), which may make it possible to characterize localized excitations (including solitons, but also including chaotic modes) generated by PDE systems. The significance to computer hardware and neurocomputing is also discussed. This mathematics--IF further developed--may also have the potential to reorganize and simplify our understanding of QFT itself--a topic of very great intellectual and practical importance. The paper concludes by describing three new possibilities for research, which will be very important to achieving these goals.

Optical soliton transmissions at 10 and 20Gbit/s over 1000km with the use of erbium-doped fiber amplifiers are described in detail. For the 10Gbit/s experiment, a bit error rate (BER) of below 110-13 was obtained with 220-1 pseudorandom patterns and the power penalty was less than 0.1dB. In the 20Gbit/s experiment optical multiplexing and demultiplexing techniques were used and a BER of below 110-12 was obtained with 223-1 pseudorandom patterns under a penalty-free condition. A new technique for sending soliton pulses over ultralong distances is presented which incorporates synchronous shaping and retiming using a high speed optical modulator. Some experimental results over 1 million km at 7.210Gbit/s are described. This technique enables us to overcome the Gordon-Haus limit, the accumulation of amplified spontaneous emission (ASE), and the effect of interaction forces between adjacent solitons. It is also shown by computer runs and a simple analysis that a one hundred million km soliton transmission is possible by means of soliton transmission controls in the time and frequency domains. This means that limit-free transmission is possible.

A new capacitor over bit-line (COB) stacked capacitor memory cell was developed using a local interconnect poly-silicon layer to arrange a capacitor contact between bit-lines. This memory cell enables usable capacitor area to increase and capacitor contact hole depth to decrease. The hemispherical grain (HSG) silicon, whose effective surface area is twice that of ordinary poly-silicon, was utilized for the storage node to increase the storage capacitance without increasing the storage node height. The feasibility of achieving a 1.8 µm2 memory cell with 30 fF storage capacitance using a 7 nm-SiO2-equivalent dielectric film and a 0.5 µm-high HSG storage node has been verified for 64 MbDRAMs by a test memory device using a 0.4 µm CMOS process.

The concentration of the electric field at the edge of the electrode has been simulated in several types of flat DRAM cell capacitors with high permittivity dielectrics. The results indicated that the permittivity of the material surrounding the edge of the electrode as well as the geometrical structure affected the concentration of the electric field. The electric field strength was minimized and most evenly distributed by utilizing the structure in which the sidewall of the capacitor dielectric was terminated at the edge of the electrode by a low-dielectric constant insulator. High-precision fabrication of the capacitor's profile is required for the minimization and uniformity of the electric field.

In this paper, a design method is described for very low sensitivity fully-balanced narrow-band band-pass switched-capacitor filters (SCF's) whose worst-case sensitivities of the amplitude responses become zero at every reflection zero. The proposed method is based on applying the low-pass to high-pass transformation, the pseudo two-path technique and the capacitance-ratio reduction technique to very low sensitivity low-pass SC ladder filters. A design example of the band-pass SCF with a quality factor Q250 is given to verify the proposed method. The remarkable advantages of this approach are very low sensitivity to element-value variations, a small capacitance spread, a small total capacitance, and clock-feedthrough noise immunity inside the passband.

Robust-fault tolerance is a property that a computational result becomes nearly equal to the correct one at the occurrence of faults in digital system. There are many cases where the safety of digital control systems can be maintained if the property is satisfied. In this paper, robust-fault-tolerant three-valued arithmetic modules such as an adder and a multiplier are proposed. The positive and negative integers are represented by the number of 1's and 1's, respectively. The design concept of the arithmetic modules is that a fault makes linearly additive effect with a small value to the final result. Each arithmetic module consists of identical submodules linearly connected, so that multi-stage structure is formed to generate the final output from the last submodule. Between the input and output digits in the submodule some simple functional relation is satisfied with respect to the number of 1's and 1's. Moreover, the output digit value depends on very small portion of the submodules including the input digits. These properties make the linearly additive effect with a small value to the final result in the arithmetic modules even if multiple faults are occurred at the input and output of any gates in the submodules. Not only direct three-valued representation but also the use of three-valued logic circuits is inherently suitable for efficient implementation of the arithmetic VLSI system. The evaluation of the robust-fault-tolerant three-valued arithmetic modules is done with regard to the chip size and the speed using the standard CMOS design rule. As a result, it is made clear that the chip size can be greatly reduced.

This paper describes design considerations for high frequency active BPFs up to 100 MHz. The major design issues for high frequency active filters are the excess phase shift in the integrators and high power consumption of the integrators. Typical bipolar transistor based transconductors such as the Gilbert gain cell and the linearized transconductor with two asymmetric emitter-coupled pairs have been analyzed and compared. It has been clarified that the power consumption of the linearized transconductor can be much smaller than that of the Gilbert gain cell because of its high transconductance to working current ratio while maintaining a signal to noise ratio of the same order. A simple high-speed fully differential linearized transconductor cell is proposed with emitter follower buffers and resistive loads for excess phase compensation. A novel gyrator based transformation for the LC ladder BPF has been introduced. This transformation has resulted in a structure with simple capacitor-coupled active resonators which exactly preserves the original transfer function. A fourth order 10.7 MHz BPF IC was designed using the proposed transconductors. It was fabricated and has demonstrated the usefulness of the proposed approach. In addition, an experimental 100 MHz second order BPF IC with Q=14 has been successfully implemented indicating the potential of the proposed approach.