We propose a CMOS image sensor that realizes wide dynamic range imaging and nonlinear representation of I/O characteristics. The proposed image sensor controls the integration time for each pixel based on the brightness distribution of objects. The histogram at the end of the integration is estimated from the early intermediate photodiode values that are read out to an external circuit. Using the estimated histogram, the imaging parameters, which control the integration time pixel-by-pixel, are optimized in the external circuit. According to the imaging parameters, the intermediate photodiode value is compared with the threshold and reset to the starting value depending on the comparison result. These processes repeat several times. At the end of the integration, the photodiode value is reconstructed by using the imaging parameters. Then, wide dynamic range images with adapted I/O characteristics are obtained. We have fabricated a prototype with a size of 6464 pixels using a 0.35-µm 2-poly 4-metal CMOS process. In this paper, we explain the principle of the proposed sensor and discuss the system architecture and its operation. The experimental results obtained using the prototype are also presented, and we verify its effectiveness.

This paper presents the processor architecture which provides much higher level dependability than the current ones. The features of it are: (1) fault tolerance and secure processing are integrated into a modern superscalar VLSI processor; (2) light-weight effective soft-error tolerant mechanisms are proposed and evaluated; (3) timing errors on random logic and registers are prevented by low-overhead mechanisms; (4) program behavior is hidden from the outer world by proposed address translation methods; (5) information leakage can be avoided by attaching policy tags for all data and monitoring them for each instruction execution; (6) injection attacks are avoided with much higher accuracy than the current systems, by providing tag trackings; (7) the overall structure of the dependable processor is proposed with a dependability manager which controls the detection of illegal conditions and recovers to the normal mode; and (8) an FPGA-based testbed system is developed where the system clock and the voltage are intentionally varied for experiment. The paper presents the fundamental scheme for the dependability, elemental technologies for dependability and the whole architecture of the ultra dependable processor. After showing them, the paper concludes with future works.

This paper proposes a novel MP3 watermarking method which is applicable to a mobile terminal with limited computational resources. Considering that in most cases the embedded information is copyright information or metadata, which should be extracted before playing back audio contents, the watermark detection process should be executed at high speed. However, when conventional methods are used with a mobile terminal, it takes a considerable amount of time to detect a digital watermark. This paper focuses on scalefactor manipulation to enable high speed watermark embedding/detection for MP3 audio and also proposes the manipulation method which minimizes audio quality degradation adaptively. Evaluation tests showed that the proposed method is capable of embedding 3 bits/frame information without degrading audio quality and detecting it at very high speed. Finally, this paper describes application examples for authentication with a digital signature.

Let Ni be the number of connected spanning subgraphs with i(n-1 i m) edges in an n-vertex m-edge undirected graph G=(V,E). Although Nn-1 is computed in polynomial time by the Matrix-tree theorem, whether Nn is efficiently computed for a graph G is an open problem (see e.g., [2]). On the other hand, whether Nn2≥ Nn-1Nn+1 for a graph G is also open as a part of log concave conjecture (see e.g., [6],[12]). In this paper, for a complete graph Kn, we give the formulas for Nn, Nn+1, by which Nn, Nn+1 are respectively computed in polynomial time on n, and, in particular, prove Nn2> Nn-1Nn+1 as well.

We propose a multiparty protocol for comparator networks which are used to compute various functions in statistical analysis, such as the maximum, minimum, median, and quartiles, for example, through sorting and searching. In the protocol, all values which are inputted to a comparator network and all intermediate outputs are kept secret assuming the presence of an honest majority. We also introduce an application of the protocol for a secure (M+1)-st price auction.

Often, the major requisites of short-range communication systems are low power consumption and low cost, rather than high data-transmission speeds. This paper proposes low-cost and extremely low-power radio communication devices that use a basic one-chip microcomputer for short-range transmission and reception. In the proposed transmitter, a rectangular wave is generated at external I/O ports as carrier by the basic one-chip microcomputer and is then filtered and radiated by an antenna circuit. In the proposed receiver, the received signal is detected by a radio IC and is subsequently digitally processed by a microcomputer with a built-in A/D converter. The proposed transmitter and receiver are demonstrated, and the system performance is experimentally evaluated.

In this paper, we propose a new mask estimation method for the computational auditory scene analysis (CASA) of speech using two microphones. The proposed method is based on a hidden Markov model (HMM) in order to incorporate an observation that the mask information should be correlated over contiguous analysis frames. In other words, HMM is used to estimate the mask information represented as the interaural time difference (ITD) and the interaural level difference (ILD) of two channel signals, and the estimated mask information is finally employed in the separation of desired speech from noisy speech. To show the effectiveness of the proposed mask estimation, we then compare the performance of the proposed method with that of a Gaussian kernel-based estimation method in terms of the performance of speech recognition. As a result, the proposed HMM-based mask estimation method provided an average word error rate reduction of 61.4% when compared with the Gaussian kernel-based mask estimation method.

In this letter, a new estimation filtering is proposed when a delay between signal generation and signal estimation exists. The estimation filter is developed under a maximum likelihood criterion using only the finite observations on the delay interval. The proposed estimation filter is represented in both matrix form and iterative form. It is shown that the filtered estimate has good inherent properties such as time-invariance, unbiasedness and deadbeat. Via numerical simulations, the performance of the proposed estimation filtering is evaluated by the comparison with that of the existing fixed-lag smoothing, which shows that the proposed approach could be appropriate for fast estimation of signals that vary relatively quickly. Moreover, the on-line computational complexity of the proposed estimation filter is shown to be maintained at a lower level than the existing one.

In MIMO systems, the channel identification is important to distinguish transmitted signals from multiple transmit antennas. One of the most typical channel identification schemes is to employ a code division multiplexing (CDM) based scheme in which a unique spreading code is assigned to distinguish both BS and MS antenna elements. However, by increasing the number of base stations and transmit antenna elements, large spreading codes and pilot symbols are required to distinguish the received power from all the connectable BS, as well as to identify all the CSI for the combination of transmitter and receiver antenna elements. Furthermore, the complexity of maximum likelihood detection (MLD) for implementation of MIMO is a considerable work. To reduce these problems, in this paper, we propose the parallel detection algorithm using multiple QR decompositions with permuted channel matrix (MQRD-PCM) with discrete pilot signal assignment and iterative channel identification for MIMO/OFDM.

A simple and successful design of initial codebook of vector quantization (VQ) is presented. For existing initial codebook algorithms, such as random method, the initial codebook is strongly influenced by selection of initial codewords and difficult to match with the features of the training vectors. In the proposed method, training vectors are sorted according to the norm of training vectors. Then, the ordered vectors are partitioned into N groups where N is the size of codebook. The initial codewords are obtained from calculating the centroid of each group. This initializtion method has a robust performance and can be combined with the VQ algorithm to further improve the quality of codebook.

The main idea in perceptual image compression is to remove the perceptual redundancy for representing images at the lowest possible bit rate without introducing perceivable distortion. A certain amount of perceptual redundancy is inherent in the color image since human eyes are not perfect sensors for discriminating small differences in color signals. Effectively exploiting the perceptual redundancy will help to improve the coding efficiency of compressing color images. In this paper, a locally adaptive perceptual compression scheme for color images is proposed. The scheme is based on the design of an adaptive quantizer for compressing color images with the nearly lossless visual quality at a low bit rate. An effective way to achieve the nearly lossless visual quality is to shape the quantization error as a part of perceptual redundancy while compressing color images. This method is to control the adaptive quantization stage by the perceptual redundancy of the color image. In this paper, the perceptual redundancy in the form of the noise detection threshold associated with each coefficient in each subband of three color components of the color image is derived based on the finding of perceptually indistinguishable regions of color stimuli in the uniform color space and various masking effects of human visual perception. The quantizer step size for the target coefficient in each color component is adaptively adjusted by the associated noise detection threshold to make sure that the resulting quantization error is not perceivable. Simulation results show that the compression performance of the proposed scheme using the adaptively coefficient-wise quantization is better than that using the band-wise quantization. The nearly lossless visual quality of the reconstructed image can be achieved by the proposed scheme at lower entropy.

The online buffer management problem formulates the problem of queueing policies of network switches supporting QoS (Quality of Service) guarantee. For this problem, several models are considered.In this paper, we focus on shared memory switches with preemption. We prove that the competitive ratio of the Longest Queue Drop (LQD) policy is (4M-4)/(3M-2) in the case of N=2, where N is the number of output ports in a switch and M is the size of the buffer.This matches the lower bound given by Hahne, Kesselman and Mansour.Also, in the case of arbitrary N, we improve the competitive ratio of LQD from 2 to 2 - (1/M) minK = 1, 2, ..., N{M/K + K - 1}.

In this paper, we present a reconfigurable processor infrastructure to accelerate Java applications, called Jaguar. The Jaguar infrastructure consists of a compiler framework and a runtime environment support. The compiler framework selects a group of Java methods to be translated into hardware for delivering the best performance under limited resources, and translates the selected Java methods into Verilog synthesizable code modules. The runtime environment support includes the Java virtual machine (JVM) running on a host processor to provide Java execution environment to the generated Java accelerator through communication interface units while preserving Java semantics. Our compiler infrastructure is a tightly integrated and solid compiler-aided solution for Java reconfigurable computing. There is no limitation in generating synthesizable Verilog modules from any Java application while preserving Java semantics. In terms of performance, our infrastructure achieves the speedup by 5.4 times on average and by up to 9.4 times in measured benchmarks with respect to JVM-only execution. Furthermore, two optimization schemes such as an instruction folding and a live buffer removal can reduce 24% on average and up to 39% of the resource consumption.

Let M(y) be a matrix whose entries are polynomial in y, λ(y) and v(y) be a set of eigenvalue and eigenvector of M(y). Then, λ(y) and v(y) are algebraic functions of y, and λ(y) and v(y) have their power series expansionsλ(y) = β0 + β1 y + + βk yk + (βj C),(1) v(y) = γ0 + γ1 y + + γk yk + (γj Cn), (2)provided that y=0 is not a singular point of λ(y) or v(y). Several algorithms are already proposed to compute the above power series expansions using Newton's method (the algorithm in [4]) or the Hensel construction (the algorithm in[5],[12]). The algorithms proposed so far compute high degree coefficients βk and γk, using lower degree coefficients βj and γj (j=0,1,,k-1). Thus with floating point arithmetic, the numerical errors in the coefficients can accumulate as index k increases. This can cause serious deterioration of the numerical accuracy of high degree coefficients βk and γk, and we need to check the accuracy. In this paper, we assume that given matrix M(y) does not have multiple eigenvalues at y=0 (this implies that y=0 is not singular point of λ(y) or v(y)), and presents an algorithm to estimate the accuracy of the computed power series βi,γj in (1) and (2). The estimation process employs the idea in [9] which computes a coefficient of a power series with Cauchy's integral formula and numerical integrations. We present an efficient implementation of the algorithm that utilizes Newton's method. We also present a modification of Newton's method to speed up the procedure, introducing tuning parameter p. Numerical experiments of the paper indicates that we can enhance the performance of the algorithm by 1216%, choosing the optimal tuning parameter p.

In this paper, a new compensation scheme and a corresponding pass element structure for a CMOS low-dropout regulator (LDO) are presented. The proposed approach effectively alleviates the strict stability constraint on the ESR of the output capacitor. Stability of a CMOS LDO with the conventional compensation requires the effective series resistance (ESR) of the output capacitor in a tunnel-like region. With the proposed design approach, an LDO can be stable using an output capacitor without ESR. A 2.5 V/150 mA LDO has been implemented using a 0.5-µm 1P2M CMOS process. The experimental results illustrate that the proposed LDO is stable with an output capacitor of 0.33 µF and no ESR.

Research on the electromagnetic compatibility of functional module composed of two independent electromagnetic relays in a hermetically sealed shell is the technical foundation for integration and miniaturization of electronic equipment in the future. In this paper, 3D finite element method (FEM) was used to analyze the dynamic characteristics of twin-type relay interfered by uniform constant magnetic field and identify the sensitive direction in which the relay was easily interfered. The models of twin-type relay in three working states were founded. Through simulation and analysis, it was found out how the operation time and electromagnetic torque of twin-type relay changed with the outer interfered magnetic field. When the relay was on the point of operation failure, the critical value of magnetic field was calculated through simulation. The simulation results of the dynamic characteristics of twin-type relay agree well with the experimental data. The conclusion in this paper is of great value for research on the electromagnetic compatibility of relay functional module.

In this letter, we propose a new histogram equalization method to compensate for acoustic mismatches mainly caused by corruption of additive noise and channel distortion in speech recognition. The proposed method employs an improved test cumulative distribution function (CDF) by more accurately smoothing the conventional order statistics-based test CDF with the use of window functions for robust feature compensation. Experiments on the AURORA 2 framework confirmed that the proposed method is effective in compensating speech recognition features by reducing the averaged relative error by 13.12% over the order statistics-based conventional histogram equalization method and by 58.02% over the mel-cepstral-based features for the three test sets.

This paper presents a new adaptive minor subspace extraction algorithm based on an idea of Peng and Yi ('07) for approximating the single minor eigenvector of a covariance matrix. By utilizing the idea inductively in the nested orthogonal complement subspaces, the proposed algorithm succeeds to relax the numerical sensitivity which has been annoying conventional adaptive minor subspace extraction algorithms for example, Oja algorithm ('82) and its stabilized version: O-Oja algorithm ('02). Simulation results demonstrate that the proposed algorithm realizes more stable convergence than O-Oja algorithm.

The IEEE 1500 standard wrapper requires that its inputs and outputs be interfaced directly to the chip's primary inputs and outputs for controllability and observability. This is typically achieved by providing a dedicated Test Access Mechanism (TAM) between the wrapper and the primary inputs and outputs. However, when reusing the embedded Network-on-Chip (NoC) interconnect instead of the dedicated TAM, the standard wrapper cannot be used as is because of the packet-based transfer mechanism and other functional requirements by the NoC. In this paper, we describe two NoC-compatible wrappers, which overcome these limitations of the 1500 wrapper. The wrappers (Type 1 and Type 2) complement each other to optimize NoC bandwidth utilization while minimizing the area overhead. The Type 2 wrapper uses larger area overhead to increase bandwidth efficiency, while Type 1 takes advantage of some special configurations which may not require a complex and high-cost wrapper. Two wrapper optimization algorithms are applied to both wrapper designs under channel-bandwidth and test-time constraints, resulting in very little or no increase in the test application time compared to conventional dedicated TAM approaches.

We have developed a prototype optical brain-computer interface (BCI) system that can be used by an operator to manipulate external, electrically controlled equipment. Our optical BCI uses near-infrared spectroscopy and functions as a compact, practical, unrestrictive, non-invasive brain-switch. The optical BCI system measured spatiotemporal changes in the hemoglobin concentrations in the blood flow of a subject's prefrontal cortex at 22 measurement points. An exponential moving average (EMA) filter was applied to the data, and then their weighted sum with a task-related parameter derived from a pretest is utilized for time-indicated control (GO-STOP) of an external object. In experiments using untrained subjects, the system achieved control patterns within an accuracy of 6 sec for more than 80% control.