Recently several researchers have proposed various methods to build intelligent stock trading and portfolio management systems using rapid advancements in artificial intelligence including machine learning techniques. However, existing technical analysis-based stock price prediction studies primarily depend on price change or price-related moving average patterns, and information related to trading volume is only used as an auxiliary indicator. This study focuses on the effect of changes in trading volume on stock prices and proposes a novel method for short-term stock price predictions based on trading volume patterns. Two rapid volume decrease patterns are defined based on the combinations of multiple volume moving averages. The dataset filtered using these patterns is learned through the supervised learning of neural networks. Experimental results based on the data from Korea Composite Stock Price Index and Korean Securities Dealers Automated Quotation, show that the proposed prediction system can achieve a trading performance that significantly exceeds the market average.

Nowadays, a rapid increase of demand on high-performance computation causes the enthusiastic research activities regarding massively parallel systems. An interconnection network in a massively parallel system interconnects a huge number of processing elements so that they can cooperate to process tasks by communicating among others. By regarding a processing element and a link between a pair of processing elements as a node and an edge, respectively, many problems with respect to communication and/or routing in an interconnection network are reducible to the problems in the graph theory. For interconnection networks of the massively parallel systems, many topologies have been proposed so far. The hypercube is a very popular topology and it has many variants. The bicube is a such topology and it can interconnect the same number of nodes with the same degree as the hypercube while its diameter is almost half of that of the hypercube. In addition, the bicube keeps the node-symmetric property. Hence, we focus on the bicube and propose an algorithm that gives a minimal or shortest path between an arbitrary pair of nodes. We give a proof of correctness of the algorithm and demonstrate its execution.

This paper presents robust optimization models for minimizing the required backup capacity while providing probabilistic protection against multiple simultaneous failures of physical machines under uncertain virtual machine capacities in a cloud provider. If random failures occur, the required capacities for virtual machines are allocated to the dedicated backup physical machines, which are determined in advance. We consider two uncertainties: failure event and virtual machine capacity. By adopting a robust optimization technique, we formulate six mixed integer linear programming problems. Numerical results show that for a small size problem, our presented models are applicable to the case that virtual machine capacities are uncertain, and by using these models, we can obtain the optimal solution of the allocation of virtual machines under the uncertainty. A simulated annealing heuristic is presented to solve large size problems. By using this heuristic, an approximate solution is obtained for a large size problem.

A vertex subset I of a graph G is called a k-path vertex cover if every path on k vertices in G contains at least one vertex from I. The K-PATH VERTEX COVER RECONFIGURATION (K-PVCR) problem asks if one can transform one k-path vertex cover into another via a sequence of k-path vertex covers where each intermediate member is obtained from its predecessor by applying a given reconfiguration rule exactly once. We investigate the computational complexity of K-PVCR from the viewpoint of graph classes under the well-known reconfiguration rules: TS, TJ, and TAR. The problem for k=2, known as the VERTEX COVER RECONFIGURATION (VCR) problem, has been well-studied in the literature. We show that certain known hardness results for VCR on different graph classes can be extended for K-PVCR. In particular, we prove a complexity dichotomy for K-PVCR on general graphs: on those whose maximum degree is three (and even planar), the problem is PSPACE-complete, while on those whose maximum degree is two (i.e., paths and cycles), the problem can be solved in polynomial time. Additionally, we also design polynomial-time algorithms for K-PVCR on trees under each of TJ and TAR. Moreover, on paths, cycles, and trees, we describe how one can construct a reconfiguration sequence between two given k-path vertex covers in a yes-instance. In particular, on paths, our constructed reconfiguration sequence is shortest.

Parallel computing essentially consists of computation and communication and, in many cases, communication performance is vital. Many parallel applications use collective communications, which often dominate the performance of the parallel execution. This paper focuses on collective communication performance to speed-up the parallel execution. This paper firstly offers our experimental result that splitting a session of collective communication to small portions (slices) possibly enables efficient communication. Then, based on the results, this paper proposes a new concept cup-stacking with a genetic algorithm based methodology. The preliminary evaluation results reveal the effectiveness of the proposed method.

This paper proposes a novel multi-layer substrate integrated waveguide (SIW) resonator loaded with asymmetric E-shaped slot-lines and shows a tri-band band-pass filter (BPF) using the proposed structure. In the previous literature, various SIW resonators have been proposed to simultaneously solve the problems of large area and high insertion loss. Although these SIWs have a lower insertion loss than planar-type resonators using a printed circuit board, the size of these structures tends to be larger. A multi-layer SIW resonator loaded with asymmetric E-shaped slot-lines can solve the above problems and realize a tri-band BPF without increasing the size to realize further miniaturization. The theoretical design method and the structural design are shown. Moreover, the configured structure is fabricated and measured for showing the validity of the design method in this paper.

Sparse code division multiple access (SCMA) is a non-orthogonal multiple access (NOMA) technology that can improve frequency band utilization and allow many users to share quite a few resource elements (REs). This paper uses the modulation of lattice theory to develop a systematic construction procedure for the design of SCMA codebooks under Gaussian channel environments that can achieve near-optimal designs, especially for cases that consider large-scale SCMA parameters. However, under the condition of large-scale SCMA parameters, the mother constellation (MC) points will overlap, which can be solved by the method of the partial dimensions transformation (PDT). More importantly, we consider the upper bounded error probability of the signal transmission in the AWGN channels, and design a codeword allocation method to reduce the inter symbol interference (ISI) on the same RE. Simulation results show that under different codebook sizes and different overload rates, using two different message passing algorithms (MPA) to verify, the codebook proposed in this paper has a bit error rate (BER) significantly better than the reference codebooks, moreover the convergence time does not exceed that of the reference codebooks.

The resistor variation can severely affect current reference sources, which may vary up to ±40% in scaled CMOS processes. In addition, such variations make the opamp design challenging and increase the design margin, impacting power consumption. This paper proposes a Time-Based Current Source (TBCS): a robust and process-scalable reference current source suitable for switched-capacitor (SC) circuits. We construct a delay-locked-loop (DLL) to lock the current-starved inverter with the reference clock, enabling the use of the settled current directly as a reference current. Since the load capacitors determine the delay, the generated current is decoupled from resistor values and enables a robust reference current source. The prototype TBCS fabricated in 28nm CMOS achieved a minimal area of 1200um2. The current variation is suppressed to half compared to BGR based current sources, confirmed in extensive PVT variation simulations. Moreover, when used as the opamp's bias, TBCS achieves comparable opamp GBW to an ideal current source.

In this paper, an algorithm based on Taylor series expansion is proposed to calculate the logarithm (log2x) of IEEE754 binary32 accuracy floating-point number by a multi-domain partitioning method. The general mantissa (1≤x<2) is multiplied by 2, 4, 8, … (or equivalently left-shifted by 1, 2, 3, … bits), the regions of (2≤x<4), (4≤x<8), (8≤x<16),… are considered, and Taylor-series expansion is applied. In those regions, the slope of f(x)=log2 x with respect to x is gentle compared to the region of (1≤x<2), which reduces the required number of terms. We also consider the trade-offs among the numbers of additions, subtractions, and multiplications and Look-Up Table (LUT) size in hardware to select the best algorithm for the engineer's design and build the best hardware device.

The shared last level cache (SLLC) in tile chip multiprocessors (TCMP) provides a low off-chip miss rate, but it causes a long on-chip access latency. In the two-level cache hierarchy, data replication stores replicas of L1 victims in the local LLC (L2 cache) to obtain a short local LLC access latency on the next accesses. Many data replication mechanisms have been proposed, but they do not consider both L1 victim reuse behaviors and LLC replica reception capability. They either produce many useless replicas or increase LLC pressure, which limits the improvement of system performance. In this paper, we propose a two-level cache aware adaptive data replication mechanism (TCDR), which controls replication based on both L1 victim reuse behaviors prediction and LLC replica reception capability monitoring. TCDR not only increases the accuracy of L1 replica selection, but also avoids the pressure of replication on LLC. The results show that TCDR improves the system performance with reasonable hardware overhead.

This paper proposes novel test techniques for high accuracy measurement of ADCs and a ramp generator on a CMOS image sensor (CIS) chip. The test circuit for the ADCs has a dual path and has an ability of multi-functional fine pattern generator that can define any input for each column to evaluate CIS specific characteristics electrically. The test circuit for the ramp generator can realize an on-chip current cell test and reject the current cell failure within 1LSB accuracy. We fabricated the test sensor using 55nm CIS process and measured the IP characteristics. Measured results show INL of 14.6LSB, crosstalk of 14.9LSB and column interference noise of 5.4LSB. These measured results agree with the designed values. By using this technique, we confirmed the accurate ADC measurement can be realized without being affected by the ambiguity of the optical input.

In this study, we investigate outdoor propagation measurements performed in an industrial park environment at 28.3GHz band. The propagation characteristics were evaluated with the measurement result regarding the path loss characteristics. Ray tracing simulation was also studied and compared with the measurement data to evaluate the quantitative accuracy of ray tracing in millimeter-wave band wireless propagations. Ray tracing, whose accuracy was evaluated based on a comparison with the measurement results, can aid in the theoretical design of the coverage area and deterministic channel modeling.

Side-channel analysis is one of the most investigated hardware Trojan detection approaches. However, nearly all the side-channel analysis approaches require golden chips for reference, which are hard to obtain actually. Besides, majority of existing Trojan detection algorithms focus on the data similarity and ignore the Trojan misclassification during the detection. In this paper, we propose a cost-sensitive golden chip-free hardware Trojan detection framework, which aims to minimize the probability of Trojan misclassification during the detection. The post-layout simulation data of voltage variations at different process corners is utilized as a golden reference. Further, a classification algorithm based on the combination of principal component analysis and Naïve bayes is exploited to identify the existence of hardware Trojan with a minimum misclassification risk. Experimental results on ASIC demonstrate that the proposed approach improves the detection accuracy ratio compared with the three detection algorithms and distinguishes the Trojan with only 0.27% area occupies even under ±15% process variations.

Rain attenuation characteristics due to typhoon passage are discussed using the Ku-band BS satellite signal observations conducted by Osaka Electro-Communication University in Neayagawa from 1988 to 2019. The degree of hourly rain attenuation due to rainfall rate is largely enhanced as typhoon passes the east side of the station, while it becomes smaller in the case of west side passage. Compared to hourly ground wind velocities of nearby AMeDAS, the equivalent path lengths of rain attenuation become larger as the wind directions approach the same angle to the satellite, while they become smaller as the wind directions approach the opposite angle to the satellite. The increase and decrease of the equivalent path lengths are confirmed in other Ku-band and Ka-band satellite paths with different azimuth angles, such as CS, SKP, and SBC. Modified equivalent path lengths calculated by a simple propagation path model including horizontal wind speeds along the same direction to the satellite agree well with the equivalent path lengths observed by each satellite. The equivalent path lengths are, for the first time, proved to be largely affected by the direction of typhoon passage and the horizontal wind velocities.

Basic characteristics for relating design and base station layout design in land mobile communications are provided through a propagation model for path loss prediction. Owing to the rapid annual increase in traffic data, the number of base stations has increased accordingly. Therefore, propagation models for various scenarios and frequency bands are necessitated. To solve problems optimization and creation methods using the propagation model, a path loss prediction method that merges multiple models in machine learning is proposed herein. The method is discussed based on measurement values from Kitakyushu-shi. In machine learning, the selection of input parameters and suppression of overlearning are important for achieving highly accurate predictions. Therefore, the acquisition of conventional models based on the propagation environment and the use of input parameters of high importance are proposed. The prediction accuracy for Kitakyushu-shi using the proposed method indicates a root mean square error (RMSE) of 3.68dB. In addition, predictions are performed in Narashino-shi to confirm the effectiveness of the method in other urban scenarios. Results confirm the effectiveness of the proposed method for the urban scenario in Narashino-shi, and an RMSE of 4.39dB is obtained for the accuracy.

A 32-bit arithmetic logic unit (ALU) is designed for a rapid single flux quantum (RSFQ) bit-parallel processor. In the ALU, clocked gates are partially replaced by clockless gates. This reduces the number of D flip flops (DFFs) required for path balancing. The number of clocked gates, including DFFs, is reduced by approximately 40 %, and size of the clock distribution network is reduced. The number of pipeline stages becomes modest. The layout design of the ALU and simulation results show the effectiveness of using clockless gates in wide datapath circuits.

The adiabatic quantum flux parametron (AQFP) is an energy-efficient, high-speed superconducting logic device. To observe the tiny output currents from the AQFP in experiments, high-speed voltage drivers are indispensable. In the present study, we develop a compact voltage driver for AQFP logic based on a Josephson latching driver (JLD), which has been used as a high-speed driver for rapid single-flux-quantum (RSFQ) logic. In the JLD-based voltage driver, the signal currents of AQFP gates are converted into gap-voltage-level signals via an AQFP/RSFQ interface and a four-junction logic gate. Furthermore, this voltage driver includes only 15 Josephson junctions, which is much fewer than in the case for the previously designed driver based on dc superconducting quantum interference devices (60 junctions). In measurement, we successfully operate the JLD-based voltage driver up to 4 GHz. We also evaluate the bit error rate (BER) of the driver and find that the BER is 7.92×10-10 and 2.67×10-3 at 1GHz and 4GHz, respectively.

The adiabatic quantum-flux-parametron (AQFP) is an energy-efficient superconductor logic device. In a previous study, we proposed a low-latency clocking scheme called delay-line clocking, and several low-latency AQFP logic gates have been demonstrated. In delay-line clocking, the latency between adjacent excitation phases is determined by the propagation delay of excitation currents, and thus the rising time of excitation currents should be sufficiently small; otherwise, an AQFP gate can switch before the previous gate is fully excited. This means that delay-line clocking needs high clock frequencies, because typical excitation currents are sinusoidal and the rising time depends on the frequency. However, AQFP circuits need to be tested in a wide frequency range experimentally. Hence, in the present study, we investigate AQFP circuits adopting delay-line clocking with square excitation currents to apply delay-line clocking in a low frequency range. Square excitation currents have shorter rising time than sinusoidal excitation currents and thus enable low frequency operation. We demonstrate an AQFP buffer chain with delay-line clocking using square excitation currents, in which the latency is approximately 20ps per gate, and confirm that the operating margin for the buffer chain is kept sufficiently wide at clock frequencies below 1GHz, whereas in the sinusoidal case the operating margin shrinks below 500MHz. These results indicate that AQFP circuits adopting delay-line clocking can operate in a low frequency range by using square excitation currents.

A Josephson parametric oscillator (JPO) is an interesting system from the viewpoint of quantum optics because it has two stable self-oscillating states and can deterministically generate quantum cat states. A theoretical proposal has been made to operate a network of multiple JPOs as a quantum annealer, which can solve adiabatically combinatorial optimization problems at high speed. Proof-of-concept experiments have been actively conducted for application to quantum computations. This article provides a review of the mechanism of JPOs and their application as a quantum annealer.

Extremely energy-efficient logic devices are required for future low-power high-performance computing systems. Superconductor electronic technology has a number of energy-efficient logic families. Among them is the adiabatic quantum-flux-parametron (AQFP) logic family, which adiabatically switches the quantum-flux-parametron (QFP) circuit when it is excited by an AC power-clock. When compared to state-of-the-art CMOS technology, AQFP logic circuits have the advantage of relatively fast clock rates (5 GHz to 10 GHz) and 5 - 6 orders of magnitude reduction in energy before cooling overhead. We have been developing extremely energy-efficient computing processor components using the AQFP. The adder is the most basic computational unit and is important in the development of a processor. In this work, we designed and measured a 16-bit parallel prefix carry look-ahead Kogge-Stone adder (KSA). We fabricated the circuit using the AIST 10 kA/cm2 High-speed STandard Process (HSTP). Due to a malfunction in the measurement system, we were not able to confirm the complete operation of the circuit at the low frequency of 100 kHz in liquid He, but we confirmed that the outputs that we did observe are correct for two types of tests: (1) critical tests and (2) 110 random input tests in total. The operation margin of the circuit is wide, and we did not observe any calculation errors during measurement.