We have proposed a quality of experience (QoE)-oriented wireless local area network (WLAN) to provide sufficient QoE to important application flows. Unlike ordinary IEEE 802.11 WLAN, the proposed QoE-oriented WLAN dynamically performs admission control with the aid of the prediction of a “loadable capacity” criterion. This paper proposes an algorithm for dynamic network reconfiguration by centralized control among multiple basic service sets (BSSs) of the QoE-oriented WLAN, in order to maximize the number of traffic flows whose QoE requirements can be satisfied. With the proposed dynamic reconfiguration mechanism, stations (STAs) can change access point (AP) to connect. The operating frequency channel of a BSS also can be changed. These controls are performed according to the current channel occupancy rate of each BSS and the required radio resources to satisfy the QoE requirement of the traffic flow that is not allowed to transmit its data by the admission control. The effectiveness of the proposed dynamic network reconfiguration is evaluated through indoor experiments with assuming two cases. One is a 14-node experiment with QoE-oriented WLAN only, and the other is a 50-node experiment where the ordinary IEEE 802.11 WLAN and the QoE-oriented WLAN coexist. The experiment confirms that the QoE-oriented WLAN can significantly increase the number of traffic flows that satisfy their QoE requirements, total utility of network, and QoE-satisfied throughput, which is the system throughput contributing to satisfy the QoE requirement of traffic flows. It is also revealed that the QoE-oriented WLAN can protect the traffic flows in the ordinary WLAN if the border of the loadable capacity is properly set even in the environment where the hidden terminal problem occurs.

In this paper, we propose an example-based single image super resolution (SR) method by l2 approximation with self-sampled image patches. Example-based super resolution methods can reconstruct high resolution image patches by a linear combination of atoms in an overcomplete dictionary. This reconstruction requires a pair of two dictionaries created by tremendous low and high resolution image pairs from the prepared image databases. In our method, we introduce the dictionary by random sampling patches from just an input image and eliminate its training process. This dictionary exploits the self-similarity of images and it will no more depend on external image sets, which consern the storage space or the accuracy of referred image sets. In addition, we modified the approximation of input image to an l2-norm minimization problem, instead of commonly used sparse approximation such as l1-norm regularization. The l2 approximation has an advantage of computational cost by only solving an inverse problem. Through some experiments, the proposed method drastically reduces the computational time for the SR, and it provides a comparable performance to the conventional example-based SR methods with an l1 approximation and dictionary training.

Patch clamp measurement technique is one of the most important techniques in the field of electrophysiology. The elucidation of the channels, nerve cells, and brain activities as well as contribution of the treatment of neurological disorders is expected from the measurement of ion current. A current-to-voltage converter, which is the front end circuit of the patch clamp measurement system is fabricated using 0.18µm CMOS technology. The current-to-voltage converter requires a resistance as high as 50MΩ as a feedback resistor in order to ensure a high signal-to-noise ratio for very small signals. However, the circuit becomes unstable due to the large parasitic capacitance between the poly layer and the substrate of the on-chip feedback resistor and the instability causes the peaking at lower frequency. The instability of a current-to-voltage converter with a high-resistance as a feedback resistor is analyzed theoretically. A compensation circuit to stabilize the amplifier by driving the N-well under poly resistor to suppress the effect of parasitic capacitance using buffer circuits is proposed. The performance of the proposed circuit is confirmed by both simulation and measurement of fabricated chip. The peaking in frequency characteristic is suppressed properly by the proposed method. Furthermore, the bandwidth of the amplifier is expanded up to 11.3kHz, which is desirable for a patch clamp measurement. In addition, the input referred rms noise with the range of 10Hz ∼ 10kHz is 2.09 Arms and is sufficiently reach the requirement for measure of both whole-cell and a part of single-channel recordings.

A multisignature (MS) scheme enables a group of signers to produce a compact signature on a common message. In analyzing security of MS schemes, a key registration protocol with proof-of-possession (POP) is considered to prevent rogue key attacks. In this paper, we refine the POP-based security model by formalizing a new strengthened POP model and showing relations between the previous POP models and the new one. We next suggest a MS scheme that achieves: (1) non-interactive signing process, (2) O(1) pairing computations in verification, (3) tight security reduction under the co-CDH assumption, and (4) security under the new strengthened POP model. Compared to the tightly-secure BNN-MS scheme, the verification in ours can be at least 7 times faster at the 80-bit security level and 10 times faster at the 128-bit security level. To achieve our goal, we introduce a novel and simple POP generation method that can be viewed as a one-time signature without random oracles. Our POP technique can also be applied to the LOSSW-MS scheme (without random oracles), giving the security in the strengthened POP model.

This paper studies the problem of recovering an arbitrarily distributed sparse matrix from its one-bit (1-bit) compressive measurements. We propose a matrix sketching based binary method iterative hard thresholding (MSBIHT) algorithm by combining the two dimensional version of BIHT (2DBIHT) and the matrix sketching method, to solve the sparse matrix recovery problem in matrix form. In contrast to traditional one-dimensional BIHT (BIHT), the proposed algorithm can reduce computational complexity. Besides, the MSBIHT can also improve the recovery performance comparing to the 2DBIHT method. A brief theoretical analysis and numerical experiments show the proposed algorithm outperforms traditional ones.

We numerically demonstrated the improvement of single-electron (SE) digital logic gates by utilizing SE input discretizers (IDs). The parameters of the IDs were adjusted to achieve SE tunneling at the threshold voltage designed for switching. An SE four-junction inverter (FJI) with an ID (ID-FJI) had steep switching characteristics between the high and low output voltage levels. The limiting temperature and the critical parameter margins were evaluated. An SE NAND gate with IDs also achieved abrupt switching characteristics between output logic levels.

Nonlinear precoding improves the downlink bit error rate (BER) performance of multi-user multiple-input multiple-output (MU-MIMO). Broadband single-carrier (SC) block transmission can improve the capability that nonlinear precoding reduces BER, as it provides frequency diversity gain. This paper considers Tomlinson-Harashima precoding (THP) as a nonlinear precoding scheme for SC-MU-MIMO downlink. In the SC-MU-MIMO downlink with frequency-domain THP proposed by Degen and Rrühl (called SC-FDTHP), the inter-symbol interference (ISI) is suppressed by transmit frequency-domain equalization (FDE) after suppressing the inter-user interference (IUI) by frequency-domain THP. Transmit FDE increases the signal variance, hence transmission performance improvement is limited. In this paper, we propose a new SC-MU-MIMO downlink with time-domain THP which can pre-remove both ISI and IUI (called SC-TDTHP) if perfect channel state information (CSI) is available. Modulo operation in THP suppresses the signal variance increase caused by ISI and IUI pre-removal, and hence the transmission quality improves. For further performance improvement, vector perturbation is introduced to SC-TDTHP (called SC-TDTHP w/VP). Computer simulation shows that SC-TDTHP achieves better BER performance than SC-FDTHP and that SC-TDTHP w/VP offers further improvement in BER performance over SC-MU-MIMO with VP (called SC-VP). Computational complexity is also compared and it is showed that SC-TDTHP and SC-TDTHP w/VP incur higher computational complexity than SC-FDTHP but lower than SC-VP.

In this paper, an analytical threshold voltage model of the strained gate-all-around MOSFET fabricated on the Si1-xGex virtual substrate is presented by solving the two-dimensional Poisson equation. The impact of key parameters such as the strain, channel length, gate oxide thickness and radius of the silicon cylinder on the threshold voltage has been investigated. It has been demonstrated that the threshold voltage decreases as the strain in the channel increases. The threshold voltage roll-off becomes severe when increasing the Ge content in the Si1-xGex virtual substrate. The model is found to tally well with the device simulator.

In this paper, we propose an efficient regularized zero-forcing (RZF) precoding method that has lower hardware resource requirements and produces a shorter delay to the first transmitted symbol compared with truncated polynomial expansion (TPE) that is based on Neumann series in massive multiple-input multiple-output (MIMO) systems. The proposed precoding scheme, named matrix decomposition-polynomial expansion (MDPE), essentially applies a matrix decomposition algorithm based on polynomial expansion to significantly reduce full matrix multiplication computational complexity. Accordingly, it is suitable for real-time hardware implementations and high-mobility scenarios. Furthermore, the proposed method provides a simple expression that links the optimization coefficients to the ratio of BS/UTs antennas (β). This approach can speed-up the convergence to the matrix inverse by a matrix polynomial with small terms and further reduce computation costs. Simulation results show that the MDPE scheme can rapidly approximate the performance of the full precision RZF and optimal TPE algorithm, while adaptively selecting matrix polynomial terms in accordance with the different β and SNR situations. It thereby obtains a high average achievable rate of the UTs under power allocation.

This paper presents a practical system which allows instructors to easily introduce 3D games utilizing smartphones in a classroom. The system consists of a PC server, a big screen and smartphone clients. The server provides 3D models, so no 3D authoring is needed when using this system. For an instructor, preparing slides of quiz-questions with the correct answers is all that is required when designing 3D games. According to a quiz specified by an instructor, this system constructs a corresponding 3D game scene. The answers students provide on their smartphones will be used to play this game. Everyone in the classroom can see this 3D game in real time on a big screen. The game illustrates how every student has reacted to a quiz. This system also introduces specialized queues for mobile interactions; a queue for commands from an instructor and a queue for data from students. The command queue has higher priority than the data queue; so that an instructor can control this system by sending commands with clicks on a smartphone. Previous studies have mostly provided specially designed teaching materials to instructors, often treating them as passive consultants. However, by using slides, already familiar to instructors, this system enables instructors to combine their own teaching materials with 3D games in the classroom. Moreover, 3D games are expected to further motivate students to actively participate in classroom activities. This system is evaluated in this paper.

Computer networks require sophisticated control mechanisms to realize fair resource allocation among users in conjunction with efficient resource usage. To successfully realize fair resource allocation in a network, someone should control the behavior of each user by considering fairness. To provide efficient resource utilization, someone should control the behavior of all users by considering efficiency. To realize both control goals with different granularities at the same time, a hierarchical network control mechanism that combines microscopic control (i.e., fairness control) and macroscopic control (i.e., efficiency control) is required. In previous works, Aida proposed the concept of chaos-based hierarchical network control. Next, as an application of the chaos-based concept, Aida designed a fundamental framework of hierarchical transmission rate control based on the chaos of coupled relaxation oscillators. To clarify the realization of the chaos-based concept, one should specify the chaos-based hierarchical transmission rate control in enough detail to work in an actual network, and confirm that it works as intended. In this study, we implement the chaos-based hierarchical transmission rate control in a popular network simulator, ns-2, and confirm its operation through our experimentation. Results verify that the chaos-based concept can be successfully realized in TCP/IP networks.

Tag collision has a negative impact on the performance of RFID systems. In this letter, we propose an algorithm termed anti-collision protocol based on improved collision detection (ACP-ICD). In this protocol, dual prefixes matching and collision bit detection technique are employed to reduce the number of queries and promptly identify tags. According to the dual prefixes matching method and collision bit detection in the process of collision arbitration, idle slots are eliminated. Moreover, the reader makes full use of collision to improve identification efficiency. Both analytical and simulation results are presented to show that the performance of ACP-ICD outperforms existing anti-collision algorithms.

Workflow nets (WF-nets for short) are a mathematical model of real world workflows. A WF-net is often updated in accordance with the change of real world. This may cause places that are redundant from the viewpoint of the behavior. Such places are called implicit. We first proposed a necessary and sufficient condition to find implicit places. Then we proved that removing of implicit places is a reduction operation which forms branching bisimilarity. We also constructed an algorithm for the reduction. Next, we applied the proposed reduction operation to WF-net refactoring. Then we showed the usefulness of the proposed refactoring with two examples.

This paper presents a novel MEMD interval thresholding denoising, where relevant modes are selected by the similarity measure between the probability density functions of the input and that of each mode. Simulation and measured EEG data processing results show that the proposed scheme achieves better performance than other traditional denoisings.

Traffic is a key aspect of everyday life. Its study, as it happens with other complex phenomena, has found in simulation a basic tool. However, the use of simulations faces important limitations. Building them requires considering different aspects of traffic (e.g. urbanism, car features, and individual drivers) with their specific theories, that must be integrated to provide a coherent model. There is also a variety of simulation platforms with different requirements. Many of these problems demand multi-disciplinary teams, where the different backgrounds can hinder the communication and validation of simulations. The Model-Driven Engineering (MDE) of simulations has been proposed in other fields to address these issues. Such approaches develop graphical Modelling Languages (MLs) that researchers use to model their problems, and then semi-automatically generate simulations from those models. Working in this way promotes communication, platform independence, incremental development, and reutilisation. This paper presents the first steps for a MDE framework for traffic simulations. It introduces a tailored extensible ML for domain experts. The ML is focused on human actions, so it adopts an Agent-Based Modelling perspective. Regarding traffic aspects, it includes concepts commonly found in related literature following the Driver-Vehicle-Environment model. The language is also suitable to accommodate additional theories using its extension mechanisms. The approach is supported by an infrastructure developed using Eclipse MDE projects: the ML is specified with Ecore, and a model editor and a code generator tools are provided. A case study illustrates how to develop a simulation based on a driver's behaviour theory for a specific target platform using these elements.

Over the last few years, Apache MapReduce has become the prevailing framework for large scale data processing. Instead of writing MapReduce programs which are too obscure to express, many developers usually adopt high level query languages, such as Hive or Pig Latin, to finish their complex queries. These languages automatically compile each query into a workflow of MapReduce jobs, so they greatly facilitate the querying and management of large datasets. One option to speed up the execution of workflows is to save the results produced previously and reuse them in the future if needed. In this paper we present SuperRack, which uses shared storage devices to store the results of each workflow and allows a new query to reuse these results in order to avoid redundant computation and hasten execution. We propose several novel techniques to improve the access and storage efficiency of the previous results. We also evaluate SuperRack to verify its feasibility and effectiveness. Experiments show that our solution outperforms Hive significantly under TPC-H benchmark and real life workloads.

This paper presents a novel low-power decoder architecture for the (36420, 32778) binary LDPC code targeting energy-efficient NAND-flash-based mobile devices. The proposed energy-scalable decoding algorithm reduces the operating bit-width of decoding function units at the early-use stage where the channel condition is good enough to lower the precision of computation. Based on a flexible adder structure, the decoding energy of the proposed LDPC decoder can be reduced by freezing the unnecessary parts of hardware resources. A prototype 4KB LDPC decoder is designed in a 65nm CMOS technology, which achieves an average decoding throughput of 8.13Gb/s with 1.2M equivalent gates. The power consumption of the decoder ranges from 397mW to 563mW depending on operating conditions.

It is known that in the selected mapping (SLM) scheme for orthogonal frequency division multiplexing (OFDM), correlation (CORR) metric outperforms the peak-to-average power ratio (PAPR) metric in terms of bit error rate (BER) performance. It is also well known that four times oversampling is used for estimating the PAPR performance of continuous OFDM signal. In this paper, the oversampling effect of OFDM signal is analyzed when CORR metric is used for the SLM scheme in the presence of nonlinear high power amplifier. An analysis based on the correlation coefficients of the oversampled OFDM signals shows that CORR metric of two times oversampling in the SLM scheme is good enough to achieve the same BER performance as four times and 16 times oversampling cases. Simulation results confirm that for the SLM scheme using CORR metric, the BER performance for two times oversampling case is almost the same as that for four and 16 times oversampling cases.

Aiming to solve the input/output (I/O) bottleneck concerning next-generation interconnections, 5×5-millimeters-squared silicon-photonics-based chip-scale optical transmitters/receivers (TXs/RXs) — called “optical I/O cores” — were developed. In addition to having a compact footprint, by employing low-power-consumption integrated circuits (ICs), as well as providing multimode-fiber (MMF) transmission in the O band and a user-friendly interface, the developed optical I/O cores allow common ease of use with applications such as multi-chip modules (MCMs) and active optical cables (AOCs). The power consumption of their hybrid-integrated ICs is 5mW/Gbps. Their high-density user-friendly optical interface has a spot-size-converter (SSC) function and permits the physical contact against the outer waveguides. As a result, they provide large enough misalignment tolerance to allow use of passive alignment and visual alignment. In a performance test, they demonstrated 25-Gbps/ch error-free operation over 300-m MMF.

In modern communication systems, it is a critical and challenging issue for existing carrier tracking techniques to achieve near-ideal carrier synchronization without the help of pilot signals in the case of symbol rate sampling and low signal-to-noise ratio (SNR). To overcome this issue, this paper proposes an effective carrier frequency and phase offset tracking scheme which has a robust confluent synchronization architecture whose main components are a digital frequency-locked loop (FLL), a digital phase-locked loop (PLL), a modified symbol hard decision block and some sampling rate conversion blocks. As received signals are sampled at symbol baud rate, this carrier tracking scheme is still able to obtain precise estimated values of carrier synchronization parameters under the condition of very low SNRs. The performance of the proposed carrier synchronization scheme is also evaluated by using Monte-Carlo method. Simulation results confirm the feasibility of this carrier tracking scheme and demonstrate that it ensures that both the rate-3/4 irregular low-density parity-code (LDPC) coded system and the military voice transmission system utilizing the direct sequence spread spectrum (DSSS) technique achieve satisfactory bit-error rate (BER) performance at correspondingly low SNRs.