We propose a transistor placement algorithm to generate standard cell layout in a two-dimensional placement style. The algorithm optimizes the one-dimensional placement in the first stage, folds the large transistors in the second stage, and optimizes the two-dimensional placement in the final stage. We also propose "cost function" based on wiring length, which closely match the cell optimization. This transistor placement algorithm has been applied to several standard cells, and demonstrated the capability to generate a two-dimensional placement that is comparable to manually designed placement.

This paper proposes "path mapping," a method of delay estimation for technology independent combinational circuits. Path mapping provides fast and accurate delay estimation using common ideas with the tree covering based technology mapping. First, path mapping does technology mapping for all paths in the circuit with minimum mapped delay. Then, it finds the largest mapped delay among all the paths in the circuit, and answers it as an estimated circuit delay. Experimental results show path mapping estimates more accurate circuit delay than unit delay, and runs much faster than the technology mapping.

A 90 GHz band planar-type superconducting mixer using Ba1-xKxBiO3 (BKBO) bicrystal junctions was fabricated on a MgO bicrystal substrate. The mixer is integrated with microwave circuits and two junctions, but we could not operate the mixer in image rejection mode because of process damage to the junction properties. However we confirmed the mixing operation; the intermediate frequency (IF) signal was observed up to 17K (LO87 GHz, RF92 GHz).

In this paper we propose a comprehensive approach to physical design based on the constraint paradigm. Bounds on the most critical circuit parasitics are automatically generated to help designers and/or physical design tools meet a set of high-level specifications. The constraint generation engine is based on constrained optimization, where various parasitic effects on interconnect and devices are accounted for and dealt with in different manners according to their statistical behavior and their effect on performance.

In this paper, we introduce a Shared Multiple Rooted XOR-based Decomposition Diagram (XORDD) to represent functions with multiple outputs. Based on the XORDD representation, we develop a synthesis algorithm for general Exclusive Sum-of-Product forms (ESOP). By iteratively applying transformations and reductions, we obtain a compact XORDD which gives a minimized ESOP. Our method can synthesize larger circuits than previously possible. The compact ESOP representation provides a form that is easier to synthesize for XOR heavy multi-level circuits, such as arithmetic functions. We have applied our synthesis techniques to a large set of benchmark circuits in both PLA and combinational formats. Results of the minimized ESOP forms obtained from our synthesis algorithm are also compared to the SOP forms generated by ESPRESSO. Among the 74 circuits we have experimented with, the minimized ESOP's have fewer product terms than those of SOP's in 39 circuits.

In computer hardware there is a constant evolution towards smaller transistor sizes. At the same time, more and more transistors are placed on one chip. Both trends make the pin limitation problem worse. Scaling down chip sizes adds to the shortage of available pins while increasing the number of transistors per chip imposes a higher need for chip terminals. The use of three-dimensional systems would alleviate this pin limitation problem. In order to decide whether the benefits of such systems balance the higher processing costs, one must be able to characterize these benefits accurately. This can be done by estimating important layout properties of electronic designs, such as space requirements and interconnection length values. For a two-dimensional placement, Donath found an upper bound for the average interconnection length that follows the trends of experimentally obtained average lengths. Yet, this upper bound deviates from the experimentally obtained value by a factor of approximately 2 which is not sufficiently accurate for some applications. In this paper, we first extend Donath's technique to a three-dimensional placement. We then compute a significantly more accurate estimate by taking into account the inherent features of the optimal placement process.

We successfully observed curent-voltage (I-V) curves which showed the behavior of intrinsic Josephson junctions using Tl2Ba2CaCu2Ox (Tl-2212) thin films on MgO substrates by structuring mesas and measuring the electrical transport properties along the c-axis. For a 55 µm2 mesa, a hysteretic I-V curve was observed up to 80 K, which showed that series-connected SIS-type junctions are formed. Compared with the critical current density (Jc) of more than 106 A/cm2 parallel to the ab-plane, an anisotropic Jc of 1.4102 A/cm2 along the c-axis was observed at 4.9 K. By focusing on the I-V curve at lower bias current, the constant voltage jumps measured at the first seven branches were estimated to be 26 mV. The normal resistance (Rnk) of a unit SIS junction was estimated to be 580 Ω by substituting the measured voltage jump in the Ambegaokar and Baratoff relation. Using the calculation for McCumber parameter (βc), the capacitance (Ck) of the unit SIS junction was estimated to be 3.610-10 F/cm2 at 77 K. The IckRnk product was estimated to be 6.4 mV and the cut-off frequency (fc1/2πRnkCk) was calculated to be 3.1 THz at 77 K. The Jc and the hysteresis decreased with an increase in the mesa area, and finally, for a 300300µm2 mesa, a resistively shunted junction (RSI) like curve without hysteresis was observed up to 98 K. A Jc of 5.6101 A/cm2 along the c-axis was observed at 6.4 K. This may be explained by the higher content of conductive grain boundaries for a larger mesa area.

A parallel IP router that uses off-the-shelf wor-kstations and interconnecting switches is presented. This router, called CORErouter-I, is a medium-grained, functionally distributed parallel system consisting of four kinds of processors for routing, routing-table searching, servicing, and line interfacing. Also discussed are issues related to the implementation of CORErouter-I, especially in terms of routing protocol processing and packet-forwarding. Performance characteristics of CORErouter-I are also clarified through several experiments performed to evaluate maximum throughput, analyze packet-forwarding time, and estimate the effect of parallel processing on the route-flapping problem.

While estimating glitches or spurious transitions is a challenge due to signal correlations, the random behavior of logic gate delays makes the estimation problem even more difficult. In this paper, we present statistical estimation of signal activity at the internal and output nodes of combinational and sequential CMOS logic circuits considering uncertainty of gate delays. The methodology is based on the stochastic models of logic signals and the probabilistic behavior of gate delays due to process variations, interconnect parasitics, etc. We propose a statistical technique of estimating average-case activity, which is flexible in adopting different delay models and variations and can be integrated with worst-case analysis into statistical logic design process. Experimental results show that the uncertainty of gate delays makes a great impact on activity at individual nodes (more than 100%) and total power dissipation (can be overestimated up to 65%) as well.

An analysis is carried out about the reflection influence on the microwave attenuation measurement for moisture content determination. A new method taking into account the reflection influence is proposed and it is proved valid by the experiment results. Using this method, the density dependence of the attenuation is measured and the measured data can be fitted well by a straight line passing through the origin. Therefore, the attenuation per unit density and propagation distance is a function which depends only on the moisture content and the function is useful to the determination of the moisture content.

This paper proposes a new approach that makes it possible for every undergraduate student to perform experiments of developing a Ipipelined RISC processor within limited time available for the course. The approach consists of 4 steps. At the first step, every student implements by himself/herself a pipelined RISC processor which is based on a given, very simple model; it has separate buses for instruction and data memory ("Harvard architecture") to avoid structural hazard, while it completely ignores data control hazards to make implementation easy. Although it is such a "defective" processor, we can test its functionality by giving object code containing sufficient amount of NOP instructions to avoid hazards. At the second step, NOP instructions are deleted and behavior of the developed processor is observed carefully to understand data and control hazards. At the third step, benchmark problems are provided, and every student challenges to improve its performance. Finally every student is requested to present how he/she improved the processor. This paper also describes a new educational FPGA board ASAver.1 which is useful for experiments from introductory class to computer architecture/system class. As a feasibility study, a 16-bit pipelined RISC processor "ASAP-O" has been developed which has eight 16-bit general purpose registers, a 16-bit program counter, and a zero flag, with 10 essential instructions.

The necessary and sufficient conditions for f (x2+x+1) and f (x2+x) to be irreducible, when f (x) is irreducible, are proved. A method that produces polynomials whose roots are linearly independent (therefore form a normal basis for a finite field) is presented.

A novel cryptographic key assignment scheme for dynamic access control in a user hierarchy is presented. Based on Rabin's public key system and Chinese remainder theorem, each security class SCi is assigned a secret key Ki and some public parameters. In our scheme, a secret key is generated in a bottom-up manner so as to reduce the computation time for key generation and the storage size for public parameters. We also show that our proposed scheme is not only secure but also efficient.

In layout design of transport-processing FPGAs, it is required that not only routing congestion is kept small but also circuits implemented on them operate with higher operation frequency. This paper extends the proposed simultaneous placement and global routing algorithm for transport-processing FPGAs whose objective is to minimize routing congestion and proposes a new algorithm in which the length of each critical signal path (path length) is limited within a specified upper bound imposed on it (path length constraint). The algorithm is based on hierarchical bipartitioning of layout regions and LUT (Look Up Table) sets to be placed. In each bipartitioning, the algorithm first searches the paths with tighter path length constraints by estimating their path lengths. Second the algorithm proceeds the bipartitioning so that the path lengths of critical paths can be reduced. The algorithm is applied to transport-processing circuits and compared with conventional approaches. The results demonstrate that the algorithm satisfies the path length constraints for 11 out of 13 circuits, though it increases routing congestion by an average of 20%. After detailed routing, it achieves 100% routing for all the circuits and decreases a circuit delay by an average of 23%.

This paper proposes the signaling network deployment for mobile networks with a goal of reducing the signaling cost and time to set up calls. In this deployment, we solve the heavy concentration of signaling traffic resulting from the centralized database used in current mobile networks. The solution exploits the features of the distributed databases, data partition, locality of mobile users, and Common Channel Signaling System No.7 (CCSS No.7) network architectures. We assume the area served by the mobile network is partitioned into a few zones. There is a database associated with each zone. A numbering database strategy is proposed in this paper for the mobiles to register at some specific nearby databases according to their mobile identification numbers. Thus, a calling party can directly locate the called party by the mobile identification number he/she dialed. This method can reduce over 95% of the location-updating cost and 70% of the location-tracking cost under a general sumulation model. We also present the implementation considerations of this strategy. This implementation is an enhancement of the routing function of the Signaling Connection Control Part in CCSS No.7 protocol stacks. With few modifications on current mobile networks, the proposed strategy can obtain very excellent results.

Field Programmable Gate Arrays (FPGA's) are important devices for rapid system prototyping. Roth-Karp decomposition is one of the most popular decomposition techniques for Look-Up Table (LUT) -based FPGA technology mapping. In this paper, we propose a novel algorithm based on Binary Decision Diagrams (BDD's) for selecting good lambda set variables in Roth-Karp decomposition to minimize the number of consumed configurable logic blocks (CLB's) in FPGA's. The experimental results on a set of benchmarks show that our algorithm can produce much better results than the similar works of the previous approaches.

We investigate performance of TCP protocol over ATM networks by using a simulation technique. As the ATM layer, we consider (1) rate-based control of the ABR service class and (2) an EPD (Early Packet Discard) technique applied to the UBR service class and (3) and EPD with per-VC accounting for fairness enhancement applied to the UBR service class. In comparison, we adopt a multi-hop network model where the multiple ATM switches are interconnected. In such a network, unfairness among connections is a possible cause of the problem due to differences of the number of hops and/or the round trip times among connections. Simulation results show that the rate-based control method of ABR achieves highest throughput and best fairness in most circumstances. However, the performance of TCP over ABR is degraded once the cell loss takes place due to the inappropriate control parameter setting. To avoid this performance degradation, we investigate the appropriate parameter set suitable to TCP on ABR service. As a result, parameter tuning can improve the performance of TCP over ABR, but limited. We therefore consider TCP over ABR with EPD enhancement where the EPD technique is incorporated into ABR. We last consider the multimedia network environment, where the VBR traffic exists in the network in addition to the ABR/UBR traffic. By this, we investigate an applicability of the above observations to a more generic model. Through simulation experiments, we find that the similar results can be obtained, but it is also shown that parameters of the rate-based congestion control must be chosen carefully by taking into account the existence of VBR traffic. For this, we discuss the method to determine the appropriate control parameters.

Satellite beam-switching problems are studied where there are m up-link beams, n down-link beams and multiple carriers per beam. By augmenting a traffic matrix with an extra row and column, it is possible to find a sequence of switching modes ((0,1)-matrices with genrally multiple unit entries in each row and column) that realize optimal transmission time. Switching modes generated are shown to be linearly independent. The number of switching modes required for an mn matrix is bounded by (m1)(n1)1. For an augmented (m1)(n1) matrix, the bound is then mn1. The bounds on the number of switching modes and the computational complexity for a number of related satellite transmission scheduling problems are lowered. In simplified form, the results (particularly the linear independence of permutation matrices generated) apply to algorithmic decomposition of doubly stochastic matrices into convex combinations of permutation matrices.

In this paper, we propose a scalable service networking architecture as a TINA-like environment for providing flexibly various mobility services. The proposed architecture provides an environment that enables the advent of service providers and rapidly introduces multimedia applications, considering networks scalability. For supporting customized mobility services, this architecture adopts a new service component, which we call Omnipresent Personal Environment Manager (OpeMgr). In order to support mobile users who move between heterogeneous networks, for instance, between the TINA-like environment and the Internet environment, we propose a structure of a gateway. In addition, the proposed architecture uses the fixed and mobile agent approaches for supporting the user's mobility, and we evaluated their performances with comparing those approaches.

A modified cryptographic key assignment scheme for the dynamic access control in a group-oriented user hierarchy is presented. In the partially ordered set (poset, for short) user hierarchy (GjGi) embedded in a group-oriented (t, n) threshold cryptosystem, the source group Gi has higher security clearance to access the information items held in the target group Gj. If a target group Gj has multipe paths reachable from a source group Gi, we must choose the least cost path to rapidly resolve the dynamic access control problem Furthermore, multiple threshold values are also considered in order to meet the different security requirements.