This paper presents two types of two-dimensional (2-D) adaptive beamforming algorithm which have high rate of convergence. One is a linearly constrained minimum variance (LCMV) beamforming algorithm which minimizes the average output power of a beamformer, and the other is a generalized sidelobe canceler (GSC) algorithm which generalizes the notion of a linear constraint by using the multiple linear constraints. In both algorithms, we apply a 2-D lattice filter to an adaptive filtering since the 2-D lattice filter provides excellent properties compared to a transversal filter. In order to evaluate the validity of the algorithm, we perform computer simulations. The experimental results show that the algorithm can reject interference signals while maintaining the direction of desired signal, and can improve convergent performance.

The basic operation characteristics of an asymmetric turnstile which transfers each electron one by one in one direction is described. A novel single electron counter circuit consisting of the asymmetric turnstiles, a load capacitor and an inverter which counts the number of high inputs is proposed. Monte Carlo circuit simulations reveal that the gate clock time of the counter circuit should be long enough to achieve allowable minimum error rate. The counter circuit implementing asymmetric single electron turnstiles is demonstrated to be applicable to a noise reduction system, a Winner-Take-All circuit and an artificial neuron circuit.

We have studied the methods to operate single electron circuits with high reliability at room temperature. By simulation, we have numerically analyzed the error mechanisms of the room-temperature operation of a 2-gate electron pump as a fundamental single electron element circuit. We have found from the results that under the room temperature condition where the ratio of the electrostatic energy to the thermal energy for a transition electron is not so large, the minimum operation error probability is obtained at the specific gate sweep time when the circuit is operated with ramp-waveform control voltages. The analyses indicate that in the shorter sweep time range, the error probability increases because the gate voltage has changed before the significant electron transition occurs, and that in the longer sweep time range, the error probability also increases due to undesired-single-transition events. The optimum sweep time is estimated statically with the relationship between desired- and undesired-single-transition rates as a function of control gate voltages. Using the optimum condition, the operation reliability is expected to be improved by a factor of 100. This estimation method has been also confirmed by the time-dependent Monte-Carlo simulation.

Parallelism on heterogeneous machines brings cost effectiveness, but also raises a new set of complex and challenging problems. This paper addresses the problem of estimating the minimum time taken to execute a program on a fine-grained parallel machine composed of different types of processors. In an earlier publication, we took the first step in this direction by presenting a graph-construction method which partitions a given program into several homogeneous parts and incorporates timing constraints due to heterogeneous parallelism into each part. In this paper, to make the method easier to be applied in a scheduling framework and to demonstrate its practical utility, we present an efficient implementation method and compare the results of its use to the optimal schedule lengths obtained by enumerating all possible solutions. Experimental results for several different machine models indicate that this method can be effectively used to estimate a program's minimum execution time.

We propose new key exchange and authentication protocols, which are efficient in protecting a poorly-chosen weak secret from guessing attacks, based on the use of a one-time pad and a strong one-way hash function. Cryptographic protocols assume that a strong secret should be shared between communication participants for authentication, in the light of an ever-present threat of guessing attacks. Cryptographically long secret would be better for security only if ordinary users could remember it. But most users choose an easy-to-remember password as a secret and such a weak secret can be guessed easily. In our previous work, we made much of introducing a basic concept and its application. In this paper, we describe our idea in more detail and propose more protocols which correspond to variants of our basic protocol using well-defined notations. Formal verification and efficiency comparison of the proposed protocols are also presented. By our scheme the password guessing attacks are defeated efficiently, and a session key is exchanged and participants are authenticated securely.

An oversampling theorem for regular sampling in wavelet subspaces is established. The sufficient-necessary condition for which it holds is found. Meanwhile the truncation error and aliasing error are estimated respectively when the theorem is applied to reconstruct discretely sampled signals. Finally an algorithm is formulated and an example is calculated to show the algorithm.

This paper proposes a method of constructing single-electron logic subsystems on the basis of the binary decision diagram (BDD). Sample subsystems, an adder and a comparator, are designed by combining single-electron BDD devices. It is demonstrated by computer simulation that the designed subsystems successfully produce, through pipelined processing, an output data flow in response to the input data flow. The operation error caused by thermal agitation is estimated. An output interface for converting single-electron transport into binary-voltage signals is also designed.

This paper proposes a new associative memory architecture using stochastic behavior in single electron tunneling (SET) devices. This memory stochastically extracts the pattern most similar to the input key pattern from the stored patterns in two matching modes: the voltage-domain matching mode and the time-domain one. In the former matching mode, ordinary associative memory operation can be performed. In the latter matching mode, a purely stochastic search can be performed. Even in this case, by repeating numerous searching trials, the order of similarity can be obtained. We propose a circuit using SET devices based on this architecture and demonstrate its basic operation with a simulation. By feeding the output pattern back to the input, this memory retrieves slightly dissimilar patterns consecutively. This function may be the key to developing highly intelligent information processing systems close to the human brain.

This paper proposes an architecture for circuit construction for developing single-electron integrated circuits based on majority logic. The majority logic gate circuit proposed consists of a capacitor array for input summation and a single-electron inverter for threshold operation. It accepts an odd number of inputs and produces the corresponding output on the basis of the principle of majority decision; it produces an output of logic "1" if the majority of the inputs is 1, and an output of "0" if the majority is 0. By combining the proposed majority gate circuits, various subsystems can be constructed with a smaller number of devices than that of Boolean-based construction. An adder and a parity generator are designed as examples. It is shown by computer simulation that the designed subsystems produce the correct logic operations. The operation error induced by thermal agitation is also estimated.

Recently reported multidimensional geometrically uniform signal constellations (L MPSK and Decomposed-Lattice constellations) are joined in the term of Generalized Permutation Alphabets (GPA). Possibility of a binary isometric labeling of GPA's is completely characterized. An algorithm for constructing generating groups of PSK-type GPA is proposed. We show that this concept, when is extended to the lattice, gives rise to a class of new coset codes which perform out best codes listed in [11].

In this paper, a threshold voltage (VT) cancellation circuit for neuron-MOS (νMOS) analog circuits is described. By connecting the output terminal of this circuit with one of the input terminals of the νMOS transistor, cancellation ofVT is realized. The circuit has advantages of ground-referenced output and is insensitive to the fluctuation of bias and supply voltages. Second-order effects, such as the channel length modulation effect, the mobility reduction effect and device mismatch of the proposed circuit are analyzed in detail. Low-power and high-swing νMOS cascode current mirror is presented as an application. Performance of the proposed circuits is confirmed by HSPICE simulation with MOSIS 2. 0 µ p-well double-poly and double-metal CMOS device parameters.

This paper proposes to apply random mapping methods of a pseudo random function to find collisions of a hash function. We test a hash function including a block cipher (see ISO/IEC 10118-2) with computers, where users can select its initial vector. In particular, the paper shows that a hash function with multiple stages generates a lot of collision hash values, so our probabilistic consideration of a small model for the hash function well explains the computational results. We show that it's feasible to find collisions between the selected messages in advance for 64-bit-size hash functions with WSs linked via an ordinary LAN (Local Area Network). Thus, it is dangerous to use the hash function -- single block mode -- defined in [6] and [7].

We analyze M,MMPP/G/1 finite queues with queue-length-threshold (QLT) scheduling policy and Bernoulli schedule where the arrival of type-1 customers (nonreal-time traffic) is Poisson and the arrival of type-2 customers (real-time traffic) is a Markov-modulated Poisson process (MMPP). The next customer to be served is determined by the queue length in the buffer of type-1 customers. We obtain the joint queue length distribution for customers of both types at departure epochs by using the embedded Markov chain method, and then obtain the queue length distribution at an arbitrary time by using the supplementary variable method. From these results, we obtain the loss probabilities and the mean waiting times for customers of each type. The numerical examples show the effects of the QLT scheduling policy on performance measures of the nonreal-time traffic and the bursty real-time traffic in ATM networks.

A multiple signature scheme proposed in [1] is proved to be insecure.

Various high-performance SOI CMOS circuits were fabricated using fully-depleted 0.25-µm gate MOSFETs on a low-dose SIMOX substrate. 2.4-Gbps operations were achieved for I/O and speed conversion circuits which are key elements in a multimedia communication LSI. LVTTL-compatible gate array LSI was developed with an ESD protection circuit which is the first one to meer the MIL standard. A 120-kG test LSI was fabricated on the gate array, and the LSI performances using three kind of technologies; 0.25-µm bulk and SIMOX and 0.5-µm bulk; were compared. A 0.25-µm SIMOX LSI was 10% faster with 35% less power dissipation compared with a 0.25-µm bulk LSI. The 0.25-µm SIMOX LSI can operate at a VDD of 1.2 V to attain the same speed as the 0.5-µm bulk LSI operating at 3.3 V, and this results in 1/40 power reduction. For the high-speed communication use, an ATM-switch LSI with 220-kG and a 110-kb memory was fabricated. A high-performance of 2.5-Gbps interface speed and 312-Mbps internal speed were achieved using 0.25-µm CMOS/SIMOX. This ATM-switch LSI has the greatest bandwidth of 40-Gbps ever reported using a one-chip ATM-switch LSI.

This paper proposes a direct-sequence spread spectrum (DS/SS) communication system with a new diversity technique designed for indoor multi-path fading channels where path diversity isn't available. In this system, the transmitter sends a same signal from multiple antennas at the same time with intentional time delays, which allows the receiver to distinguish and combine the signals from different antennas. We also consider the combination of this scheme with the conventional receiving antenna diversity for additional diversity gain. Furthermore, it is found that the use of the multiple transmitting antennas decreases the effect of the multiple access interference.

This paper propeses advanced multi-stage interference canceller systems (MSICS) wihch can estimate radio channels with precision in the direct sequence code division multiple access (DS-CDMA) systems. For the accurate channel estimations, we propose a novel radio channel estimation method specified by the following two signal processing methods. One is the radio channel estimation using both pilot and information signals. The other is the correction of estimated radio channels using adaptation algorithm based on the least mean square method (LMS). The results of our computer simulation indicate that the cell capacity of the advanced MSICS in serial and parallel structure can be increased by about 1.8 and 1.3 times over that of a receiver which does not has a canceller, respectively. Moreover, the advanced MSICS in serial and parallel structure can reduce the required Eb/No by about 1.2 dB and 1.6 dB at a BER of 10-3 compared to the Eb/No of a basic MSICS, respectively.

A computer-aided low-power design methodology for very high-speed Si bipolar standard cell LSI is described. In order to obtain Gbit/s-speed operation, it features a pair of differential clock channels inside cells and a highly accurate static timing analysis for back annotation. A newly developed CAD-based power optimization scheme minimizes cell currents while maintaining circuit speed. A 5.6 k gate SDH signal-processing LSI operating at 1.6 Gbit/s with only 3.9 W power consumption demonstrates the effectiveness of this design technology.

The performance of a constrained (that is, minimal order) Yule-Walker (CYW) single tone frequency estimator is studied. A closed form expression for the asymptotic error variance is derived. It is shown that CYW does not satisfactorily utilize the informaiton in data, and estimators with improved performance are proposed. Simulation results which lend support to the theoretical findings are included.

Many digital signal processors (DSPs) employ indirect addressing using address registers (ARs) to indicate their memory addresses, which often leads to overhead. This paper presents methods to efficiently allocate addresses for variables in a given program so that overhead in AR update operations is reduced. Memory addressing model is generalized in such a way that AR can be updated at the codes without memory accesses. An efficient memory address allocation is obtained by a method based on the graph linearization algorithm, which takes account of the number of possible AR update operations for every memory access. In order to utilize multiple ARs, methods to assign variables into ARs are also investigated. The proposed methods are applied to the compiler for µPD77230 (NEC) and generated codes for several examples prove effectiveness of these methods.