In this paper, a systematic method which generates the micro-architecture of Application Specific Instruction Processor (ASIP) is proposed. Different from previous works, the data path and control path are generated from the instruction sequence which is generated by translating the compiled assembly code. A graphical representation method called Register Transfer Graph (RTG) is introduced to describe the micro-operations of instruction sequence. To achieve high performance, we perform micro-operation level scheduling which dynamically assigns the micro-operations of instruction sequence to the control steps. By transforming the architecture using synthesis parameters, design space is explored more extensively. Connection cost is minimized by removing the inefficient data transfer paths.

A clock-feedthrough (CFT) compensation technique using a dummy cell is valid when the CFT current from a switched-current (SI) memory cell is signal-independent. Based on this idea, a SI dummy cell appropriate for the S2I cell is developed. Simulations show that the CFT rejection ratio as high as 60dB is attainable over the temperature range from -30 to 80 with this architecture. The CFT-compensated SI cell proposed here is, therefore, quite usuful for high-accuracy, current-mode signal processing.

Microwave power transistors for high efficiency applications are surveyed briefly. Methodologies for microwave transistor power amplifier circuit design are discussed. Microwave transistor power amplifiers are categorized according to their operation into classes A, AB, B, C, and F, and some preliminary results on output power, power efficiency, and power gain for the amplifiers in various classes are provided by an analysis using an ideal transistor model. Circuit conditions controlling the voltage and current waveforms and device parameters such as the knee voltage in the device current-voltage characteristics are discussed for viewpoint of realizing high-efficiency power amplifier operation. A practical power amplifier design is considered with respect to the device characteristics and circuit conditions.

This paper describes the effectiveness of stream-oriented data-driven scheme for achieving autonomous fault management of hyper-distributed systems such as networks based on the Telecommunications Information Networking Architecture (TINA). TINA, whose specifications are in the finalizing phase within TINA-Consortium, is aiming at achieving interoperability and reusability of telecom applications software and independent of underlying technologies. However, to actually implement TINA network, it is essential to consider the technology constraints. Especially autonomous fault management at run-time is crucial for distributed network environment because centralized control using global information is very difficult. So far many works have been done on so-called off-line management but runtime management of service failure seems immature. This paper proposes introduction of stream-oriented data-driven processors to the autonomous fault management at runtime in TINA based distributed network environment. It examines the features of distributed network applications and technology requirements to achieve fault management of those distributed applications such as effective multiprocessing of surveillance, testing, reconfiguration in addition to ordinary processing.

A pipelined adaptive digital filter (ADF) architecture based on a two-dimensional least mean square algorithm is proposed. This architecture enables the ADF to be operated at a high clock rate and reduction of the required amount of hardware. To achieve this reduction we introduce a new building unit, called a block, and propose implementing the pipelined ADF using the block, Since the number of blocks in a cell is adjustable, we derive a condition for satisfying given specifications. We show the smallest number of blocks and the corresponding delay can be determined by using the proposed method.

Several multiuser detectors have been recently proposed to combat multiple-access interference and near-far problem for CDMA systems. The performance of a multi-user receiver in combining the decorrelating decision-feedback scheme for a synchronous DS/CDMA system is considered. Using the Gaussian approximation on the multiple-access interference and amplitude estimation errors, we derive a closed form expression for the BER performance of the decorrelating decision-feedback detector in single-path Rayleigh fading channel and power controlled system. And, we show that our analysis agrees with the results of simulations. A modified decision-feedback detector is also proposed and analyzes. Numerical results show that the modified dicision-feedback detector proposed in this paper results in enhanced performance.

We discuss a new decoder for the multiple-valued signed-digit number, using a current-mode CMOS transistor-oriented circuit structure. In this paper, a new decoding method with the selective summation of a redundantly represented addend "O = [-1 r]" is proposed, where r is the radix and the addend is applied to each digit with a negative value and any consecutively higher digit takes which has a value of O. A newly designed literal linear circuit is realized, which has a current-switch function that makes independently the short path when each digit has a value of O. Through the parallel connections of these current swiches, the same addend signal at the lower digit is transmitted in a higher speed, The decoder circuit is tested by using the general circuit simulation software SPICE and the circuit characteristics of the selective summation of a redundantly represented O addend and the output results of the SD decoding operation were simulated. We also evaluated the decoder circuit in terms of the processing speed and the circuit size.

This paper describes a new Vector Sum Excited Linear Prediction (VSELP) coder with very low complexity. The method, called regular pulse VSELP (RP-VSELP), is based on regular pulse basis vectors with mutually orthonormal property. In this Approach, a very efficient vector-sum codebook is constructed from a set of mutually orthonormal regular pulse bassis vectors and enables us to simplify the codebook search without additional degradation of synthesized speech compared with that of the conventional VSELP. The regular pulse basis vectors are explicitly orthonormalized by means of the Gram-Schmidt procedure. To enhance the speech quality of the RP-VSELP speech coder, perceptually weighted distortion measure between the input and the synthesized speech is utilized in an iterative closedloop training process of the regular pulse basis vectors. It is shown that speech quality is improved by the training process. Experimental results demonstrate that the proposed method produces the synthesized speech quality comparable to that of the VSELP scheme at the bit-rate of 4.8 Kbps.

In contrast to previous algorithms for reconfiguring processor arrays under the assumption that spare rows and columns are placed on the perimeter of the array or on fixed positions, our new algorithm employs movable and partitionable spare rows and columns. The objective of moving and partitioning spare rows and/or columns is the elimination of faulty processors each of which is blocked in all directions to spare processors. The results of our computer simulation indicate that reconfigurability can significantly be improved.

To enhance fabrication yield for processor arrays, many reconfiguration schemes for replacing faulty processing elements (PE's) with spare PE's have been proposed. An array grid model based on single-track switches is one of such models. For this model, some algorithms for reconfiguring processor arrays have been proposed. However, any algorithm which can reconfigure the array, whenever the array is reconfigurable, has not been proposed as yet. This paper describes reconfiguration methods of processor arrays with faulty PE's. The methods use indirect replacements for reconfiguring arrays. First, we introduce a concept of fatal fault pattern, which makes an array unreconfigurable. Then, for the reconfiguration method with fixed spare arrangement, efficient spare arrangements are given by evaluating the probability of an occurring fatal fault pattern. Furher, we present reconfiguration algorithm with relocating spare. In the algorithm, fatal fault patterns are eliminated by relocating spare. Computer simulations show that the method has good performance of reconfiguration.

We present a high performance AlGaAs/GaAs power HBT with very low thermal resistance for digital cellular phones. Device structure with emitter air-bridge is utilized and device layout is optimized to reduce thermal resistance based on three-dimensional thermal flow analysis, and in spite of a rather thick substrate (100 µm), which achieved a low thermal resistance of 23/W for a multi-finger (440 µm240 fingers) HBT. This 40 finger HBT achieved power added efficiency (PAE) of over 53%, 29.1 dBm output power (Pout) and high associated gain (Ga) of 13.5 dB with 50 kHz adjacent channel leakage power (Padj) of less than -48 dBc under a 948 MHz π/4-shifted QPSK modulation with 3.4 V emitter-collector voltage. We also investigated the difference of RF performance between two bias modes (constant base voltage and current), and found which mode is adequate for each stage in several stage power amplifier for the first time.

Users of computer communication systems and their requirements are rapidly increasing and changing. It is desirable to have a development method which helps to make small changes in a design of a system to obtain another system which satisfies new requirement changes. We propose a flexible synthesis method which adopts designers' requirement changes in formal protocol specifications designed in LOTOS.

An optical array imaging system has been presented in previous articles. In this system, first, the object is illuminated with laser light sequentially from each of the array elements and the reflected field is detected as interferogram. The interferograms obtained are then spatially heterodyne-detected on a computer to extract the signal components, that is, array data. Then, the eigenvector of the largest eigenvalue is derived by applying the power method to the array data and it is beam-steered to get images of the object. The algorithm gives good images for most objects, but it fails to work for some objects. It was shown that using a subset of the array data may solve the problem, but that finding the corresponding optimum subaperture is quite time-consuming. In this paper, first, the integral equation describing the system is solved for a general class of object, to make clear the conditions for the eigenvector to form a sharp beam. Second, the imaging algorithm is sped up to a great degree by optimizing only the illuminating aperture in a coarse fashion. Third, the rate of convergence of the power method is adaptively estimated in the algorithm to make the eigenvector derivation reliable. Finally the improved algorithm is investigated using both computer-generated and experimentally obtained array data.

Event-related are the kind of signals that are time-related to a given event. In this work, we will study the effect of bias and overlapping noise on Fourier linear combiner (FLC)-based filters, and its implication on filtering event-related signals. We found that the bias alters the weights behaviour, and therefore the filter output, and we discuss solutions to the problem of spectral overlap.

This paper describes novel techniques for analyzing power MOSFETs. Since the gate width of power MOSFETs is much larger than that of power MESFETs or HJFETs, an appropriate device design to suppress matching circuit losses is needed. These losses and the intrinsic device characteristics are analyzed employing the proposed techniques, which are based on large-signal simulations. Also, new formulas describing the dependence of saturated output power on gate width are derived to perform loss-minimized design. These techniques are applied to the design of power MOSFETs for GSM cellular telephones. As a result, an output power of 35.5 dBm with a power-added efficiency of 55% and a power gain of 10.5 dB at 900 MHz have been achieved.

A neural network approach called the "Gradual Neural Network (GNN)" for the time slot assignment problem in the TDM multicast switching system is presented in this paper. The goal of this NP-complete problem is to find an assignment of packet transmission requests into a minimum number of time slots. A packet can be transmitted from one source to several destinations simultaneously by its replication. A time slot represents a switching configuration of the system with unit time for each packet transmission through an I/O line. The GNN consists of the binary neural network and the gradual expansion scheme. The binary neural network satisfies the constraints imposed on the system by solving the motion equation, whereas the gradual expansion scheme minimizes the number of required time slots by gradually expanding activated neurons. The performance is evaluated through simulations in practical size systems, where the GNN finds far better solutions than the best existing altorithm.

Private networks are becoming globalized and more complicated through LAN-WAN interconnection. While WANs are managed by CMIP, LANs are managed by SNMP. To achieve end-to-end management, the integration of CMIP-based and SNMP-based management is important. We have developed an MI (Management Integration) platform for CMIP-based and SNMP-based management. It provides OSI SMF (Systems Management Function)-based unified basic management services to upper level applications regardless of the differences between CMIP-based and SNMP-based management. It achieves this with two modules: a management information transfer integration module that mainly covers protocol and data format differences between them, and a basic management module that covers functional differences. The translation of management information in the former module can be changed flexibly because the translation is based on an external script file. The latter module has additional SMF-like functions for the management of SNMP agents in addition to SMF manager role functions, etc. Prototype evaluation has demonstrated the feasibility of the MI platform.

As the Asynchronous Transfer Mode (ATM) technology comes to be used widely, the Telecommunications Management Network (TMN) over ATM networks becomes an important issue. Since TMN uses the OSI protocols including the Common Management Information Protocol (CMIP), it is required to implement CMIP communication over ATM networks. In order to realize OSI over ATM, ITU-T SG13 has standardized the Service Specific Coordination Function for Connection Oriented Network Service (SSCF-CONS), Service Specific Connection Oriented Protcol (SSCOP), and the Synchronization and Coordination Function (SCF). We have developed the CMIP software over ATM networks adopting these protocols. The CMIP software is designed so that it achieves both high throughput for large data transfer and short response time for small message exchange. The software adopts the implementation mechanisms commonly applied for protocol modules to reduce the overheads for controlling OSI protocol modules, and some protocol specific mechanisms especially for protocols with heavy processing overheads, i.e. SSCOP and CMIP. The performance evaluation shows that the developed CMIP software achieves more than 200 message exchanges per second for messages whose length is 64 Byte long, and achieves about 36 Mbps throughput for transferring data whose length is more than 100 KByte.

A GaAs SPDT switch IC operating at a low power supply voltage of 2.7 V has been developed for use in 1.9 GHz band personal handy phone system (PHS). In combination with MESFETs with low on-resistance and high breakdown voltage, the switch IC adopts parallel-LC resonant circuits and utilizes both stacked FETs and an additional shunt capacitor at the receiver side in order to realize low insertion loss, high isolation and low distortion characteristics. An insertion loss of 0.55 dB and an isolation of 35.8 dB were obtained at 1.9 GHz. The IC also achieved an output power of 25.0 dBm at 1 dB gain compression point, a second order distortion of -54.3 dBc and an adjacent channel leakage power of -66 dBc at 600 kHz apart from 1.9 GHz at 19 dBm output power.

A small-sized three-stage GaAs power module has been developed for portable digital radios using M-16QAM modulation. This module has exhibited typical P1dB of 10 W with PAE of 48% and a power gain of 35 dB at a low supply voltage of 6.5 V in 1.453-1.477 GHz band. The volume of the module is only 1.5 cc, which is one of the smallest value in 10 W class modules ever reported. In order to realize the reduced size and the high power performances simultaneously, the module has employed new power divider/combiner circuits with significant features of the reduced occupation area, the improved isolation properties and the function of second-harmonic control.