The performance of synchronous VLSI system is limited by the speed of the global clock which is further constrained by the clock skew. Self-timed design technique, based on the Muller model, improves performance by eliminating the global clock. In order to prevent hazard, a self-timed system should satisfy certain assumptions and timing constraints, therefore special cells are required. The novel Self-timed Cell Library is designed for 1.2µm CMOS technology which contains Muller C-elements, DCVSL circuits, latches and delay elements. It is very useful because: (1) It avoids any possible violations of the assumptions and timing constraints since all cells are custom designed; (2) It provides a fast and reliable model for self-timed system verification using either SPICE simulator or Verilog simulator; (3) It is flexible since it is compatible with an existing Standard Cell Library. In this paper, the library is described. Moreover, the simulated and measured cell characteristics are compared. Using the library, two [18] [81] matrix multipliers employing (1) DCVSL technique, and (2) micropipeline technique have been implemented as design examples and the results are compared. In addition, this paper also demonstrates the benefits of custom-layouted C-elements and a new way to realize delay element for micropipeline. The last but not least, two new HCCs are also proposed.

This paper describes what happens when the silicon layer is extremely thinned. The discussion shows that quantum mechanical short-channel effects impose limits on the down-scaling of MOSFET/SOI devices. However, thinning the silicon layer should bring new possibilities such as mobility enhancement, velocity overshoot enhancement, suppression of band-to-band tunneling, suppression of impact ionization and so on. Furthermore, the non-stationary energy transport in extremely miniaturized ultra-thin MOSFET/SOI devices is also addressed from the viewpoint of hot-carrier immunity. Related device physics are also discussed in order to consider the design methodology for contemporary MOSFET/SOI devices and new device applications for the future.

In the data path circuits of asynchronous systems, logical faults may first manifest as undetectable, transient wrong codewords, in spite of encoding the inputs and the outputs and proper organization which enables the faults to be propagated to the primary outputs in the form of non-codewords. Due to this, the conventional methods of concurrent error detection (CED) using the logic (voltage) monitoring is not effective. In this paper, we suggest a mixed-signal approach to achieve CED for a class of asynchronous circuits, known as self-timed circuits. First, we show that it is impossible to guarantee the CED using logic monitoring of the primary outputs in spite of proper encoding and organization of self-timed circuits. Then, we discuss different manifestations of single stuck-at faults occurring during normal operation in these circuits. Finally, we present the feasibility of achieving CED using a built-in current sensor (BICS) along with encoding techniques.

This paper proposes a synthesis method to obtain speed-independent asynchronous circuits directly from signal transition graph (STG) specifications with single cycle signals which can be non-persistent and have free-choice operations. The resulting circuits are implemented with basic gates and asynchronous latches, and operate correctly under finite but unbounded gate delays and the zero wire delay assumptions. The proposed method introduces 5 types of lock relations to implement a non-persistent STG. A non-persistent STG can be implemented if every non-persistent signal to a signal t is super-locked with t. The resulting circuits are optimized by extracting of literals, mapping onto asymmetric C-elements, etc. Experimental results show that the proposed synthesis method outperforms the existing synthesis systems such as SYN and SIS.

This paper deals with minimization of ESOPs (exclusive-or sum-of-products) which represent symmetric functions. Se propose an efficient simplification algorithm for symmetric functions, which guarantees the minimality for some subclass of symmetric functions, and present the minimum ESOPs for all 6-variable symmetric functions.

Heavy-ion-induced soft errors (single event upset) in submicron silicon-on-insulator (SOI) MOSFETs under space environmental conditions are studied over the temperature range of 100-400 K using three-dimensional device simulator with full-temperature models. The temperature dependence of the drain collected charge is examined in detail when a heavy-ion strikes the gate center perpendicularly. At very low temperatures, SOI MOSFETs have very high immunity to the heavy-ion-induced soft errors. In particular, alpha-particle-induced soft errors hardly occur at temperatures below 200 K. As the temperature increases, the collected charge shows a marked rate of increase. The problem of single event upset in SOI MOSFETs becomes more serious with increasing working temperature. This is because the induced bipolar mechanism is a main factor to cause charge collection in SOI MOSFETs and the bipolar current increases exponentially with increasing temperature. At room and high temperatures, the drain collected charge is strongly dependent on channel length and SOI film thickness.

The quality of ELTRAN wafers has been improved by pre-injection in epitaxial growth, surface treatment just before bonding, high temperature annealing at bonding, high selective etching and hydrogen annealing. The pre-injection reduces defects. The surface treatment eliminates edge-voids. The high temperature bonding dramatically reduces voids all over the wafer. Hydrogen annealing is very effective for surface flattening and boron out-diffusion. In particular, the edge-void elimination by the surface treatment just before bonding is greatly effective for enlarging the SOI area and reduces the edge exclusion down to only two mm. The gate oxide integrity is well evaluated. This process promises high yield and through-put, because each of the steps can be independently optimized.

In this paper, we discuss on accuracy of power dissipation medels for CMOS VLSI circuits. Some researchers have proposed several efficient power estimation methods for CMOS circuits. However, we do not know how accurate they are because we have not established a method to compare the estimated results of power consumption with power consumption of actual VLSI chips. To evaluate the accuracy of several kinds of power dissipation models in chip-level, block-level and gate-lebel etc., we have been (i) Measuring power consumtion of actual microprocessors, (ii) Estimating power consumption with several kinds of power dissipation models, and (iii) Comparing (i) with (ii). The experimental results show as follows: (1) Power estimation at gate level is accurate enough. (2) Estimating power of a clock tree independently makes estimation more accurate. (3) Area of each functional block is a good approximation of load capacitance of the block.

We are working on an algorithm to optimize the logic circuits that can be realized on the super fine-grain parallel processing architecture. As a part of this work, we have developed an inverter reduction algorithm. This algorithm is based on modeling logic circuits as dynamical systems. We implement the algorithm in the PARTHENON system, which is the high level synthesis system developed in NTT's laboratories, and evaluate it using ISCAS85 benchmarks. We also compare the results with both the existing algorithm of PARTHENON and the algorithm of Jain and Bryant.

Signal Transition Graphs (STG's) are Petri nets, which were introduced to represent a behavior of asynchronous circuits. To derive logic functions from an STG, the reachability graph should be constructed. In the verification of STG's some method based on an Occurrence net (OCN) and its prefix, called an unfolding, has been proposed. OCN's can represent both causality and concurrency between two nodes by net structure. In this paper, we propose a method to derive a logic function by generating sub state space of a given STG using the structural properties of OCN.

In this paper, in order to achieve the low power consumption of programmable divider in a PLL frequency synthesizer, we propose a new prescaler method for low power consumption. A fixed prescaler is inserted in front of the (N +1/2) programmable divider which is designed based on the new principle. The divider ratio in the loop does not vary at all even if such a prescaler is utilized. Then the permissible delay periods of a programmable divider can be extended to two times as long as the conventional method, and the low power consumption and low cost in a PLL frequency synthesizer have been achieved.

The present paper clarifies that the variance of the maximum likelihood estimator (MLE) of a parameter does not reach the Cramer-Rao lower bound (CRLB) when fitting a straight-line to observed two-dimensional data. In addition, the variance of the MLE can be shown to be equal to the CRLB only if observed noise reduces to a one-dimensional Gaussian variable. For most practical applications, it can be assumed that noise is added only to the range direction. In this case, the MLE is clearly an asymptotically effective estimator. However, even if we assume such a noise model, ML line-fitting to the data from many points of view has a high computational cost. The present paper proposes an alternative fitting method in order to provide a cost-effective unbiased estimator. The reliability of this new method is analyzed statistically and by computer simulation.

We consider single machine problems involving both specific and generalized due dates simultaneously. We show that a polynomial time algorithm exists for the problem of minimizing max {Lmax, LHmax}, where Lmax and LHmax are the maximum lateness induced by specific and generalized due dates, respectively. We also show that a simple efficient algorithm exists for the problem of minimizing the maximum lateness induced by due dates which are natural generalization of both specific and generalized due dates. In addition to the algorithmic results above, we show that the problems of minimizing max {LHmax, -Lmin} and max{Lmax, -LHmin} are NP-hard in the strong sense, where Lmin and LHmin are the minimum lateness induced by specific and generalized due dates, respectively.

In this paper, we give a concrete example of a 10-bit video rate ADC and introduce the effect of top-down design methodology with analog-HDL from the viewpoint of utilization techniques. First, we explain that analog top-down design methodology can improve chip performance by optimizing the architecture. Next, we concretely discuss the importance of modeling and verification. Verification of the full system does not require extracting all the information for each block at the transistor level in detail. The flexible verification method that we propose can provide good and fast full chip verification. We think analog top-down disign methodology will become increasingly more important from now on because "system-on-chip" requires one chip mixed-signal system LSIs.

For L 2, M 8, and transmission rate R = (log2M-1) bit/sym, a method for constructing GU trellis codes with L MPSK constellations is proposed and it is shown that the maximally achievable free distance is twice larger than it was previously reported for GU codes. Basides being geometrically uniform, these codes perform as good as Pietrobon's non-GU trellis codes with multidimensional MPSK constellations.

In this paper we describe the implementation of complex architectures using a general design approach for two-phase asynchronous systems. This fundamental approach, called Event Controlled Systems, can be used to widely extend the utility of two phase systems. We describe solutions that we have developed that dramatically improve the performance of static and dynamic-logic asynchronous pipelines, and briefly describe a complex microprocessor designed using ECS.

The parasitic bipolar effect in a 200-V-class thin-film SOI power MOSFET fabricated using the silicon wafer direct bonding wafer was investigated by electrical measurement, two-dimensional process simulation, emission microscopy, and 2-dimensional thermal analysis. It degraded the breakdown voltage of the thin-film SOI power MOSFET and was caused by the increase in the sheet resistance of the body contact region. Photo emission analysis indicated that excess holes recombined in the n+-source region.

A high-speed silicon-on-insulator (SOI) of a 1/8 frequency divider and a 64-bit adder were realized using an optimized gate-overlapped LDD and a self-aligned titanium silicide (TiSi2) source-drain structure. The advantages of the delay time and power consumption were analyzed by circuit simulation. The maximum operation frequency of the SOI divider is 2.9 GHz at 3.3 V. The SOI divider operates about 1.6 times faster than the bulk-Si divider. The power consumption of the SOI divider at the maximum operating frequency is about 60% of that of the bulk divider. On the other hand, the speed of the SOI adder is 1.9 nsec at 3.3 V. The SOI adder speed is about 1.3 times faster than the bulk adder. The power consumption of the SOI adder is about 80% of that of the bulk divider. It was found that the high speed, low power features of the SOI divider were due to the pass transistor which had low junction capacitance and little substrate bias effects, in addition to the low wiring capacitance and low fanout capacitance compared to the bulk adder. As a result, it is suggested that SOI circuits using pass transistor have a potential for GHz level systems and it is expected they will be applied to handy communication systems and portable computers used in the multimedia era.

In accordance with the diffusion of applications, such as the Desk Top Publishing system, the Document Formatting system and the Document Editing system, it is easy to make a document by using a computer. However, as for allocating the diagrams (figures and tables), there are few document processing systems able to allocate diagrams on the appropriate places automatically. In a document processing system it is a very important issue to allocate diagrams on the most suitable places. This paper defines the criteria for allocating diagrams on the suitable positions by investigating published papers. These criteria concern 1) the order of diagrams to be allocated, 2) the stability of the diagram allocations, 3) the distance between the diagram and the location of the corresponding first reference in the text, 4) the allocation balance of diagrams in a text, 5) the restricted areas where diagrams shouldn't be allocated, 6) the allocation priorities between diagrams of different width. Moreover, this paper proposes a method for deciding the diagram allocations satisfying the above criteria automatically and fast on document formatting systems. In this case we have limited its application to one type of ducuments, which is papers. Especially, this method can skillfully allocate diagrams of different width on the page by reallocating the diagrams and texts within it, and can allocate diagrams over the document uniformly.

This study proposes an amplitude limiting type spread spectrum communication to be applied to extremely low power radio wave communicaion and evaluates capability of the code division multiplex. First, changes in output from the correlation device, maximum power, and in allowable noise power are compared by computer simulation for the case where the number of multiplex channels is increased. Second, possible relationship between noise intensity and error rate is measured by actual loading experiments using a device developed for trial purpose. Third, majority decision logic is proposed for the said device to realize amplitude limiting type code division multiplex easily. When the amplitude is limited, the maximum power can be controlled at about 2 dB, and channels with more than half of the number of spread sign can be used. It is revealed that, in the spread spectrum, alteration of the number of multiplex channels is made easy by application of this method.