A suggestion for creating an excitable/oscillatory field with solid-state material is proposed. In essence, the idea is to make a spatial array of "mesoscopic particles" with the characteristics of a first-order phase transition. A theoretical computation shows that an auto-wave, or excitable wave, is generated in such an excitable field. A simple example of using this system as a diode in information flow is given.

In this paper, we propose a method to construct structure models of articulated objects from multiple local observations of their motion using state transition analysis of local geometric constraints. The object model is constructed by a bottom-up approach with three levels. Each level groups sensor data with a constraint among local features observed by the sensor, and constructs the local model. If the sensor data in current model conflict, the model is reconstructed. In each level, the first level estimates a local geometric feature from the local sensor data (eg. edge, feature point) The second level estimates a rigid body from the local geometric feature. The third level estimates an object from the rigid bodies. In the third level, the constraint between rigid bodies is estimated by transition states, which are motions between rigid bodies. This approach is implemented on a blackboard system.

We present a comparison of correlated failures for multiversion software using community error recovery (CER) and software breeding (SB). In CER, errors are detected and recovered at checkpoints which are inserted in all the versions of the software. SB is analogous to the breeding of plants and animals. In SB, versions consist of loadable modules, and a driver exchanges the modules between versions to detect and eliminate faulty modules. We formulate reliability models to estimate the probability of failure for software using either CER or SB. Our reliability models assume failures in the checkpoints in CER and the driver in SB. We use beta-binomial distribution for modeling correlated failures of versions, because much of the evidence suggests that the assumption that failures in versions occur independently is not always true. Our comparison indicates that multiversion software using SB is more reliable than that using CER when the probability of failure in the checkpoints in CER or the driver in SB is 10-7.

A model for estimating the bending loss of 1.3 µm zero-dispersion single-mode fibers at 1.58 µm from the value at 1.55 µm is investigated experimentally and theoretically. An approximated equation for estimating the bending loss ratio of 1.58 µm to 1.55 µm is proposed, which provides good agreement with the experimental results.

This paper presents a 4-valued content-addressable memory (CAM) for fully parallel template-matching operations in real-time cellular logic image processing with fixed templates. A universal literal is essential to perform a multiple-valued template-matching operation. It is decomposed of a pair of a threshold operation in a CAM cell and a logic-value conversion shared by CAM cells in the same column of a CAM cellular array, which makes a CAM cell function simple. Since a threshold operation together with a 4-valued storage element can be designed by using a single floating-gate MOS transistor, a high-density 4-valued universal-literal CAM with a single-transistor cell can be implemented by using a multi-layer interconnection technology. It is demonstrated that the performance of the proposed CAM is much superior to that of conventional CAMs under the same function.

A self-learning analog neural network LSI with non-volatile analog memory which can be updated with more than 13-bit resolution has been designed, fabricated and tasted for the first time. The non-volatile memory is attained by a new floating-gate MOSFET device that has a charge injection part and an accumulation part separated by a high resistance. We also propose a partially-serial weight-update architecture in which the plural synapse circuits use a weight-update circuit in common to reduce the circuit area. A prototype chip fabricated using a 1.3-µm double-poly CMOS process includes 50 synapse elements and its computational power is 10 MCPS. The weights can be updated at a rate of up to 40 kHz. This chip can be used to implement backpropagation networks, deterministic Boltzmann machines, and Hopfield networks with Hebbian learning.

In this paper a novel narrow-band bandpass filter with an output pair of analytic signals is presented. Since it is based on the complex analog filter, both synthesis and response characteristics of this filter are different from conventional bandpass filters. In the design of this filter, the frequency shift method is employed and the conventional lowpass to bandpass frequency transformation is not required. The analysis and examples show that the output signal pair of the proposed filter possesses same filtering characteristics and a 90 degree phase shifting characteristics in the passband. Therefore, the proposed filter will be used for a single sideband (SSB) signal generator without quadrature generator.

A new multiple-valued current-mode (MVCM) integrated circuit using a switched current-source control technique is proposed for a 1.5 V-supply high-speed arithmetic circuit with low-power dissipation. The use of a differential logic circuit (DLC) with a pair of dual-rail inputs makes the input voltage swing small, which results in a high driving capability at a lower supply voltage, while having large static power dissipation. In the proposed DLC using a switched current control technique, the static power dissipation can be greatly reduced because current sources in non-active circuit blocks are turned off. Since the gate of each current source is directly controlled by using a multiphase clock whose technique has been already used in dynamic circuit design, no additional transistors are required for currentsource control. As a typical example of arithmetic circuits, a new 1.5 V-supply 5454-bit multiplier based on a 0.8µm standard CMOS technology is also designed. Its performance is about 1.3 times faster than that of a binary fastest multiplier under the normalized power dissipation. A prototype chip is also fabricated to confirm the basic operation of the proposed MVCM integrated circuit.

A sparse memory access architecture which is proposed to achieve a high-computational-speed neural-network LSI is described in detail. This architecture uses two key techniques, compressible synapse-weight neuron calculation and differential neuron operation, to reduce the number of accesses to synapse weight memories and the number of neuron calculations without incurring an accuracy penalty. The test chip based on this architecture has 96 parallel data-driven processing units and enough memory for 12,288 synapse weights. In a pattern recognition example, the number of memory accesses and neuron calculations was reduced to 0.87% that needed in the conventional method and the practical performance was 18 GCPS. The sparse memory access architecture is also effective when the synapse weights are stored in off-chip memory.

We propose an interactive identification scheme based on the quadratic residue problem. Prover's identity can be proved without revealing his secret information with only one accreditation. The proposed scheme requires few computations in the verification process, and a small amount of memory to store the secret information, A digital signature based on this scheme is proposed, and its validity is then proved. Lastly, analysis about the proposed scheme is presented at the end of the paper.

This paper describes content addressable memory (CAM) -based hardware that serves as a highly parallel, compact and real-time image-processing system. The novel concept of a highly-parallel integrated circuits and system (HiPIC), in which a large-capacity CAM tuned for parallel data processing is a key element, is introduced. Several hardware algorithms for highly-parallel image processing based on a HiPIC with a CAM are presented in order to demonstrate that the HiPIC concept is effective for compact and real-time image processing. Two kinds of HiPIC-dedicated CAM have been developed. One is embedded on a 0.5-µm CMOS gate array. An embedded CAM up to 64 kbit and logic up to 40 kgate can be integrated on a single chip. The other is a 0.5-µm CMOS full-custom CAM LSI tuned for parallel data processing. A fully-parallel 336-kbit CAM LSI has been successfully developed. The HiPIC concept and CAM-based hardware described here promises to be an important step towards the realization of a compact and real-time image-processing system.

We have developed an SIMD-type neural-network processor (NEURO4) and its software environment. With the SIMD architecture, the chip executes 24 operations in a clock cycle and achieves 1.2 GFLOPS peak performance. An accelerator board, which contains four NEURO4 chips, achieves 3.2 GFLOPS. In this paper we describe features of the neural network chip, accelerator board, software environment and performance evaluation for several neural network models (LVQ, BP and Hopfield). The 3.2 GFLOPS neural network accelerator board demonstrates 1.7 GCPS and 261 MCUPS for Hopfield networks.

Device design to reduce the abnormal operation due to the floating body effect was investigated for 0.2µm fully depleted SOI-MOSFETs, by use of a two-dimensional device simulator. It was found that the critical drain voltage and the critical multiplication factor for the floating body effect strongly depend on the potential profile which is related to the doping concentration. Based on simulation results, a nonuniformly doped structure is proposed for optimizing the potential profile to reduce the floating body effect. The applicable voltage of this structure was found to be 40% higher than that of the uniformly doped structure. A simple model is also derived to explain the above result.

A clock-feedthrough (CFT) compensation technique using a dummy cell is valid when the CFT current from a switched-current (SI) memory cell is signal-independent. Based on this idea, a SI dummy cell appropriate for the S2I cell is developed. Simulations show that the CFT rejection ratio as high as 60dB is attainable over the temperature range from -30 to 80 with this architecture. The CFT-compensated SI cell proposed here is, therefore, quite usuful for high-accuracy, current-mode signal processing.

This paper describes novel techniques for analyzing power MOSFETs. Since the gate width of power MOSFETs is much larger than that of power MESFETs or HJFETs, an appropriate device design to suppress matching circuit losses is needed. These losses and the intrinsic device characteristics are analyzed employing the proposed techniques, which are based on large-signal simulations. Also, new formulas describing the dependence of saturated output power on gate width are derived to perform loss-minimized design. These techniques are applied to the design of power MOSFETs for GSM cellular telephones. As a result, an output power of 35.5 dBm with a power-added efficiency of 55% and a power gain of 10.5 dB at 900 MHz have been achieved.

This paper describes a concept of the quasioptical spatial power combining technique and its demonstration of active integrated antenna arrays with strong coupling as an actual example of high efficient combiner in high frequencies. Some configurations of the arrays such as a 3-element linear array and a 33 array are designed with a circuit and electromagnetic simulator. In order to predict the operating frequencies, large signal FET model parameters are determined from measured small signal S-parameters.

We have been studying on subthreshold characteristics of SOI (Silicon-On-Insulator) MOSFET's in terms of substrate bias dependence using a one-dimensional subthreshold device simulator based on Poisson equation in an SOI multilayer structure for estimating structural parameters of real devices. Here, we consider the quantum mechanical effects in the electron inversion layer of thin SOI MOSFET's, such as the two-dimensionally quantized electron states and transports, with a self-consistent solver of Poisson and Schrodinger equations and a mobility model by the relaxation time approximation. From results of simulations, we found a significant difference between this model and the classical model and concluded that the quantum mechanical effects need to be considered in analizing thin-film SOI devices.

Microwave power transistors for high efficiency applications are surveyed briefly. Methodologies for microwave transistor power amplifier circuit design are discussed. Microwave transistor power amplifiers are categorized according to their operation into classes A, AB, B, C, and F, and some preliminary results on output power, power efficiency, and power gain for the amplifiers in various classes are provided by an analysis using an ideal transistor model. Circuit conditions controlling the voltage and current waveforms and device parameters such as the knee voltage in the device current-voltage characteristics are discussed for viewpoint of realizing high-efficiency power amplifier operation. A practical power amplifier design is considered with respect to the device characteristics and circuit conditions.

A small-sized three-stage GaAs power module has been developed for portable digital radios using M-16QAM modulation. This module has exhibited typical P1dB of 10 W with PAE of 48% and a power gain of 35 dB at a low supply voltage of 6.5 V in 1.453-1.477 GHz band. The volume of the module is only 1.5 cc, which is one of the smallest value in 10 W class modules ever reported. In order to realize the reduced size and the high power performances simultaneously, the module has employed new power divider/combiner circuits with significant features of the reduced occupation area, the improved isolation properties and the function of second-harmonic control.

In OSI management, we utilize a scope parameter in Common Management Information Service (CMIS) that enables us to operate multiple Managed Objects (MOs) at one CMIS operation, so that we may reduce the number of communications between a manager and an agent. The more the number of MOs increases, the harder it is to find optimal combinations of scopes. In an existing approximation algorithm for finding optimal combinations of scopes, there are restrictions on the structure of a naming tree for the algorithm to work efficiently and the lower bound of its approximation ratio, n/4, grows in proportion to the number of MOs, n. This paper proposes a new approximation algorithm that removes the restriction on the structure of a naming tree and significantly improves the approximation ratio to (1 + ln n) in the upper bound, by keeping the same time complexity as the existing algorithm.